V DMA BLOCK: HSDMA
(1) SRAM
Example: When 2 (RD)/1 (WR) wait cycles are inserted
BCLK
A[23:0] | addr |
#CExx
#RD
#WRH/#WRL
#DMAACK
#DMAEND
Figure 2.8 #DMAACK/#DMAEND Signal Output Timing (SRAM)
(2) Burst ROM
Example: When
BCLK
A[23:2] |
| addr[23:2] |
|
|
A[1:0] | "00" | "01" | "10" | "11" |
#CE10(9)
D[15:0]
#RD
#DMAACK
#DMAEND
Figure 2.9 #DMAACK/#DMAEND Signal Output Timing (Burst ROM)
(3) DRAM
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
A[11:0] | ROW | COL #1 | COL #2 |
#RASx
#CAS
#RD
#WR
#DMAACK
#DMAEND
Figure 2.10 #DMAACK/#DMAEND Signal Output Timing (DRAM)
EPSON | S1C33210 FUNCTION PART |