III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS

I/O Memory of Input Ports

Table 9.2 shows the control bits of the input ports.

Table 9.2 Control Bits of Input Ports

Register name

Address

Bit

Name

Function

 

Setting

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

K5 function

00402C0

D7–4

–

reserved

 

 

–

 

–

–

Undefined when read.

select register

(B)

D3

CP4

CP4

1

–

 

0

CP4

0

R/W

Always set to 0.

 

 

D2

CFK52

K52 function selection

1

#ADTRG

 

0

K52

0

R/W

 

 

 

D1

CFK51

K51 function selection

1

#DMAREQ1

 

0

K51

0

R/W

 

 

 

D0

CFK50

K50 function selection

1

#DMAREQ0

 

0

K50

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K5 input port

00402C1

D7–5

–

reserved

 

 

–

 

–

–

0 when being read.

data register

(B)

D4

–

–

1

–

 

0

–

–

R

Undefined when read.

 

 

D3

CP4D

CP4 data

1

High

 

0

Low

–

R

 

 

 

D2

K52D

K52 input port data

 

 

 

 

 

–

R

 

 

 

D1

K51D

K51 input port data

 

 

 

 

 

–

R

 

 

 

D0

K50D

K50 input port data

 

 

 

 

 

–

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K6 function

00402C3

D7

CP3

CP3

1

–

 

0

CP3

0

R/W

Always set to 0.

select register

(B)

D6

CP2

CP2

1

–

 

0

CP2

0

R/W

 

 

 

D5

CP1

CP1

1

–

 

0

CP1

0

R/W

 

 

 

D4

CP0

CP0

1

–

 

0

CP0

0

R/W

 

 

 

D3

CFK63

K63 function selection

1

AD3

 

0

K63

0

R/W

 

 

 

D2

CFK62

K62 function selection

1

AD2

 

0

K62

0

R/W

 

 

 

D1

CFK61

K61 function selection

1

AD1

 

0

K61

0

R/W

 

 

 

D0

CFK60

K60 function selection

1

AD0

 

0

K60

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

K6 input port

00402C4

D7

CP3D

CP3 data

1

High

 

0

Low

–

R

 

data register

(B)

D6

CP2D

CP2 data

 

 

 

 

 

–

R

 

 

 

D5

CP1D

CP1 data

 

 

 

 

 

–

R

 

 

 

D4

CP0D

CP0 data

 

 

 

 

 

–

R

 

 

 

D3

K63D

K63 input port data

 

 

 

 

 

–

R

 

 

 

D2

K62D

K62 input port data

 

 

 

 

 

–

R

 

 

 

D1

K61D

K61 input port data

 

 

 

 

 

–

R

 

 

 

D0

K60D

K60 input port data

 

 

 

 

 

–

R

 

CFK52–CFK50: K5[2:0] function selection (D[2:0]) / K5 function select register (0x402C0)

CFK63–CFK60: K6[3:0] function selection (D[3:0]) / K6 function select register (0x402C3)

Selects the function of each input-port pin.

Write "1": Used for peripheral circuit

Write "0": Input port pin

Read: Invalid

When a bit of the CFK register is set to "1", the corresponding pin is set for use with the peripheral circuit (see Table 9.1). The pins for which register bits are set to "0" can be used as general-purpose input ports.

At cold start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset.

K52D–K50D: K5[2:0] input port data (D[2:0]) / K5 input port data register (0x402C1)

K63D–K60D: K6[3:0] input port data (D[3:0]) / K6 input port data register (0x402C4)

The input data on each input port pin can be read from this register.

Read "1": High level

Read "0": Low level

Write: Invalid

The pin voltage of each input port can be read out "1" directly when the voltage is high (VDD) or "0" when the voltage is low (VSS) respectively.

Since this register is a read-only register, writing to the register is ignored.

When the ports set for A/D converter input are read, the value obtained is always "0".

S1C33210 FUNCTION PART

EPSON

B-III-9-3