V DMA BLOCK: HSDMA (High-Speed DMA)

Address increment/decrement control

The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] is used to set this function.

S0IN[1:0]: Ch. 0 memory address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226)

S1IN[1:0]: Ch. 1 memory address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236)

S2IN[1:0]: Ch. 2 memory address control (D[D:C]) / Ch. 2 high-order source address set-up register (0x48246)

S3IN[1:0]: Ch. 3 memory address control (D[D:C]) / Ch. 3 high-order source address set-up register (0x48256)

SxIN = "00": address fixed (default)

SxIN = "01": address decremented without initialization

SxIN = "10": address incremented with initialization

SxIN = "00": address incremented without initialization

Refer to the explanation in "Setting the Registers in Dual-Address Mode".

D0IN[1:0] is not used in single-address mode.

Enabling/Disabling DMA Transfer

The HSDMA transfer is enabled by writing "1" to the enable bit HSx_EN.

HS0_EN: Ch. 0 enable (D0) / Ch. 0 enable register (0x4822C)

HS1_EN: Ch. 1 enable (D0) / Ch. 1 enable register (0x4823C)

HS2_EN: Ch. 2 enable (D0) / Ch. 2 enable register (0x4824C)

HS3_EN: Ch. 3 enable (D0) / Ch. 3 enable register (0x4825C)

However, the control information must always be set correctly before enabling a DMA transfer. Note that the control information cannot be set when HSx_EN = "1".

When HSx_EN is set to "0", HSDMA requests are no longer accepted.

When a DMA transfer is completed (transfer counter = 0), HSx_EN is reset to "0" to disable the following trigger inputs.

S1C33210 FUNCTION PART

EPSON

B-V-2-7