III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
HDLC Communications Mode
Overview
The HDLC communications mode processes HDLC frames for data transfers with PDC devices supporting packets. For a transmit operation, this mode transmits an opening flag pattern, the data from a
For a receive operation, this mode waits for an opening flag pattern, saves the data following it into a
This mode sends four types of interrupt requests to the CPU: HDLC transmit interrupts, HDLC receive interrupts, HDLC extra source status (HDLC_ES) interrupts, and HDLC special condition (HDLC_SP) interrupts.
For communications macro select (MCRS) register (D[1:0]/0x200000) settings other than
The MIPORT[1:0] bits in the communications block input port data register (D[1:0]/0x020000C) track the input levels for the DSR and RI pins.
Frame Format
Figure 10.13 summarizes the HDLC serial data signal format for HDLC communications.
The receive circuit supports sharing between the closing flag pattern and the next opening flag pattern. It also supports "0" sharing for sequential flag patterns.
Flag | Address Field | Control Field | Data field | FCS (CRC) | Flag |
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'01111110' | 8 bits | 8 bits | (arbitrary length) | 16 bits | '01111110' |
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Figure 10.13 HDLC Communications Basic Frame Format
FCS (CRC) Checking
HDLC communications uses the following FCS (CRC) polynomial for validating frame data integrity.
The FCS (CRC) calculation applies to everything from the address through data fields.
Output Port Control
For communications macro select (MCRS) register (D[1:0]/0x200000) settings other than
Input Port Control
Input Port Monitoring The MIPORT[1:0] bits in the communications block input port data register (D[1:0]/0x020000C) track the input levels for the DSR and RI pins. Note that the block does not store these values internally.
In this mode as in others, setting the GOUTE bit in the communications block input port data register (D7/0x020000C) to "1" connects the RI input to the GOUT output pin.
Note: Bits in the communications block modem status register (0x020002A) also track the input levels for the DSR and RI pins as well as transitions for triggering interrupt requests with changes in pin states.
EPSON | S1C33210 FUNCTION PART |