4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
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| Setting |
| Init. | R/W | Remarks | |||
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Communications | 0200028 | – | – |
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| – |
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| – | – | 0 when being read. | |
block CP4 | (HW) | D4 | CP4EN4 | Map UINT4 interrupt requests to CP4 | 1 | Enable | 0 |
| Disable | 0 | R/W | CP4= CP4EN4*UINT4 | ||
interrupt select |
| D3 | CP4EN3 | Map UINT3 interrupt requests to CP4 | 1 | Enable | 0 |
| Disable | 0 | R/W | +CP4EN3*UINT3 | ||
register |
| D2 | CP4EN2 | Map UINT2 interrupt requests to CP4 | 1 | Enable | 0 |
| Disable | 0 | R/W | +CP4EN2*UINT2 | ||
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| D1 | CP4EN1 | Map UINT1 interrupt requests to CP4 | 1 | Enable | 0 |
| Disable | 0 | R/W | +CP4EN1*UINT1 | ||
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| D0 | CP4EN0 | Map UINT0 interrupt requests to CP4 | 1 | Enable | 0 |
| Disable | 0 | R/W | +CP4EN0*UINT0 | ||
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Communications | 020002A | – | – |
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| – |
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| – | – | 0 when being read. | |
block modem | (HW) | D11 | RI | RI input status |
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| 1 | RI="L" | 0 |
| RI="H" | X | R |
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status register |
| D10 | CTS | CTS input status |
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| 1 | CTS="L" | 0 |
| CTS="H | X | R |
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| D9 | DCD | DCD input status |
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| 1 | DCD="L" | 0 |
| DCD="H" | X | R |
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| D8 | DSR | DSR input status |
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| 1 | DSR="L" | 0 |
| DSR="H" | X | R |
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| D7 | SDRI | RI input status 1 → | 0 |
| 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. |
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| D6 | SURI | RI input status 0 → | 1 |
| 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. |
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| D5 | SDCTS | CTS input status 1 → |
| 0 | 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. |
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| D4 | SUCTS | CTS input status 0 → |
| 1 | 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. |
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| D3 | SDDCD | DCD input status 1 → | 0 | 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. | |
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| D2 | SUDCD | DCD input status 0 → | 1 | 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. | |
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| D1 | SDDSR | DSR input status 1 → | 0 | 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. | |
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| D0 | SUDSR | DSR input status 0 → | 1 | 1 | Changed | 0 |
| No change | 0 | R/W | Write "1" to clear. | |
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Communications | 020002C | – | – |
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| – |
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| – | – | 0 when being read. | |
block modem | (HW) | D7 | EDRI | Enable SDRI interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
| ||
status interrupt |
| D6 | EURI | Enable SURI interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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enable register |
| D5 | EDCTS | Enable SDCTS interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D4 | EUCTS | Enable SUCTS interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D3 | EDDCD | Enable SDDCD interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D2 | EUDCD | Enable SUDCD interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D1 | EDDSR | Enable SDDSR interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D0 | EUDSR | Enable SUDSR interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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Communications | 020002E | – | – |
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| – |
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| – | – | 0 when being read. | |
block modem | (HW) | D1 | DTR | DTR output level |
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| 1 | DTR="H" | 0 |
| DTR="L" | 0 | R/W | Only valid for UART |
control register |
| D0 | RTS | RTS output level |
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| 1 | RTS="H" | 0 |
| RTS="L" | 0 | R/W | operation |
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Communications | 0200032 | – | – |
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| – |
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| – | – | 0 when being read. | |
block debugging | (HW) | D0 | STOP | Debugging HOLD input control | 1 | HOLD input | 0 |
| No input | 0 | R/W |
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@ mode register |
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PDC interrupt | 0200100 | – | – |
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| – |
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| – | – | 0 when being read. | |
register | (HW) | D1 | INTE | Enable PDC interrupts | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D0 | PDCINT | PDC interrupt flag |
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| 1 | Request pending | 0 |
| No interrupts | X | R/W | Write "1" to clear |
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PDC command | 0200102 | – | – |
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| – |
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| – | – | 0 when being read. | |
register | (HW) | D2 | TXBS | PDC transmit buffer select | 1 | Buffer B | 0 |
| Buffer A | 0 | R/W |
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| D1 | TXEN | Enable PDC transmit |
| 1 | Enable | 0 |
| Disable | 0 | R/W |
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| D0 | RXEN | Enable PDC receive |
| 1 | Enable | 0 |
| Disable | 0 | R/W |
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PDC status | 0200104 | – | – |
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| – |
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| – | – | 0 when being read. | |
register | (HW) | D7 | CRCER1 | PDC receive | 1 | CRC error | 0 |
| No error | X | R |
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| D6 | CRCER2 | PDC receive | 1 | CRC error | 0 |
| No error | X | R |
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| – | – |
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| – |
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| – | – | 0 when being read. | |
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| D1 | RXBB | Receive buffer B status | 1 | Input available | 0 |
| No input | X | R |
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| D0 | RXBA | Receive buffer A status | 1 | Input available | 0 |
| No input | X | R |
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PHS transmit | 0200200 | – | – |
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| – |
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| – | – | 0 when being read. | |
control register | (HW) | D7 | TXINTE | Enable PHS transmit interrupt | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| – | – |
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| – |
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| – | – | 0 when being read. | |
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| D1 | TXBS | PHS transmit buffer select Enable | 1 | Buffer B | 0 |
| Buffer A | 0 | R/W |
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| D0 | TXEN | PHS transmit |
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| 1 | Enable | 0 |
| Disable | 0 | R/W |
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PHS transmit | 0200202 | – | – |
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| – |
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| – | – | 0 when being read. | |
status register | (HW) | D7 | TXINT | PHS transmit interrupt flag | 1 | Request pending | 0 |
| No interrupts | 0 | R/W | Write "1" to clear | ||
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| – | – |
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| – |
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| – | – | 0 when being read. | |
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PHS receive | 0200204 | – | – |
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| – |
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| – | – | 0 when being read. | |
control register | (HW) | D7 | RXINTE | Enable PHS receive interrupt | 1 | Enable | 0 |
| Disable | 0 | R/W |
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| – | – |
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| – |
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| – | – | 0 when being read. | |
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| D0 | RXEN | Enable PHS receive |
| 1 | Enable | 0 |
| Disable | 0 | R/W |
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PHS receive | 0200206 | – | – |
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| – |
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| – | – | 0 when being read. | |
status register | (HW) | D7 | RXINT | PHS receive interrupt flag | 1 | Request pending | 0 |
| No interrupts | 0 | R/W | Write "1" to clear | ||
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| – | – |
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| – |
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| – | – | 0 when being read. | |
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| D2 | CRCER | PHS receive CRC error flag | 1 | CRC error | 0 |
| No error | X | R |
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| D1 | RXBS | PHS receive buffer |
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| 1 | Buffer B | 0 |
| Buffer A | X | R |
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| D0 | – | – |
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| – |
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| – | – | 0 when being read. |
EPSON | S1C33210 PRODUCT PART |