Intel 210200-002 manual SUB Subtractsub

SUB SUBTRACTSUB

Encoding:

Memory or Register Operand and Register Operand:

100101 0 d w I mod reg rim I

if d = 1 then LSRC = REG, RSRC = EA, DEST = REG else LSRC = EA, RSRC = REG, DEST = EA

Immediate Operand from Memory or Register Operand:

11 OOOOOsw Imod 101 rim I data Idata if s:w=011

LSRC = EA, RSRC = data, DEST = EA

Immediate Operand from Accumulator:

I 001 011 0 w I data I data if w=1 I

if w = 0 then LSRC = AL, RSRC = data, DEST = AL else LSRC = AX, RSRC = data, DEST = AX

SUB Operands	Clocks"	Transfers Bytes SUB Coding Example
register, register	3	-	2	SUB CX, BX
register, memory	9(13) + EA	1	2-4	SUB DX, MATH_TOTAL [SI]
memory, register	16(24) + EA	2	2-4	SU B [BP '+2], CL
accumulator, immediate	4	-	2-3	SUB AL, 10
register, immediate	4	-	3-4	SUB SI, 5280
memory, immediate	17(25) +EA	2	3-6	SUB [BP].BALANCE, 1000

*b(w): where b denotes the number of clock cycles for byte operands and w denotes the number of-clock cycles for word operands.

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