Intel 210200-002 manual Rdyinput~~

HARDWARE DESIGN

time will only result in the insertion of one or more wait states.

RDY1 and RDY2

one wait state is selected. The flip-flop is cleared by ALE, enabling RDY to the 8284A.

To generate a stable READY signal to satisfy the 8088's setup hold times, the 8284A pro- vides two separate system ready inputs (RDYI and RDY2) and a single synchron- ized ready output (READY) for the CPU.

The RDY inputs are enabled with separate active LOW access enables (AENI, AEN2) to select one of the two ready signals. The system ready inputs to the 8284A (RDYI, RDY2) must be valid 35ns (TRI VCL) before T3 and AEN must be valid 60ns before T3.

For a system using only one RDY input, the associated AEN is tied to ground while the other AEN is connected to 5 volts through lK ohms (Fig. 3-21). If the system generates a LOW active ready signal, it can be connected to one of the 8284A's AEN inputs, if the additional setup time required by the AEN input is satisfied. In this case, the associated RDY input would be tied HIGH (Fig. 3-22).

Single Wait State Generator

Most memory and peripheral devices that fail to operate at the maximum CPU frequency typically require only one wait state.

The circuit in Figure 3-23 is an example of a simple wait state generator. The system ready line is driven low whenever a device requiring

eLK

If no wait states are required, the flip-flop remains HIGH. If the system ready is driven LOW, the flip-flop toggles on the LOW to HIGH clock transition of T2 to force one wait state. The next LOW to HIGH clock transition toggles the flip-flop again to indi- cate ready, and allow completion of the machine cycle. Further changes in the state of the flip-flop will not affect the machine cycle. The cycle allows approximately lOOns for chip select decode and conditioning of the system ready.

Interrupts

The iAPX 88 has a simple and versatile inter- rupt system. Interrupts may be triggered by devices external to the CPU or by software interrupt instructions or, under certain condi- tions, by the CPU itself.

Every interrupt is assigned a type code that identifies it to the CPU. The type code is used by the CPU to point to a location in the memory based interrupt vector table contain- ing the address of the interrupt routine.

This interrupt vector table can contain up to 256 vectors for different interrupt types (Fig. 3-25).

RDYINPUT~~

READY _______________________~ ~,____________

OUTPUT

Figure 3-20.Normally Not READY Wait State Timing

3-18