Intel 210200-002 manual ClK

HARDWARE DESIGN

In the minimum mode 8088 CPU, the number of control outputs is limited by the number of pins available on the 40 pin pack- age. The maximum mode iAPX 88 system gets around this limitation by using the 8288

bus controller to generate several of the sys- tem control signals (Fig. 3-30). This frees up several 8088 pins to support multiprocessing functions not available in minimum mode systems.

ClK

HOLD

HlDA

Figure 3-29. HOlD/HlDA Timing

D

8288 BUS

LCONTROllERClK

Vce

r 1

MN/MX

So

-=l=-

8284A

.... ClK

So

INTA

COMMAND BUS

~ RES

[ - READY

S1

S1

MRDC

[ - RESET

S2

S2

MWTC

J

r --- DEN

10RC

~

10WC

CLOCK

DT/R"

r - ALE

GENERATOR

8088

CPU

II

~ STB

8283

lliDRESSBU[ 1

.-

>

8282

\

A19-A8

ADDRESS

OR

ADrADol<

ADDRESS/DATA

)

8286

0

0

•

L,

OE

1/0

i

MEMORY

PERIPHERAL

DATA

DATA

~ OE

OR

DATA BUS

\

8287

-'

>

Figure 3-30.iAPX 88 Using Maximum Mode

3-26