SUPPLEMENT
HOW ARE MACHINE CYCLES, INTERRUPTS, AND DIRECT MEMORY ACCESS RELATED?
Machine Cycles
As the microcomputer program executes, data is transferred to and from memory and 110 devices. Each time the CPU transfers data between itself and one of the other parts of the system, we call this the execution of a machine cycle (or "bus cycle"). Machine cycles include operations like instruction fetch, memory read, memory write, read from an input port, or a write to an output port. The timing of these operations is coor- dinated by the CPU clock signal derived from CPU timing sources from an external crystal or other frequency source.
At the beginning of a machine cycle, the CPU issues a binary code to the address bus to identify the memory location or 1/0 device to be accessed. Next, the CPU issues an activity command on the control bus. Third,the CPU either receives or transmits data over the data bus.
Following the data transfer, the CPU pre- pares to issue the next memory or 1/0 address for the next machine cycle. In this manner, the CPU cycles through the pro- grammed instructions, performing logical arithmetic and 110 operations as required.
The CPU keeps track of the instruction sequence with the program counter register containing the binary address of the next instruction in memory.
Normally, the program counter is incre- mented after a given instruction is executed. The CPU automatically fetches instructions from memory, decodes them, and executes them in sequence, until the program ends, or, until special instructions tell the CPU to exe- cute instructions in other parts of program memory.
Certain situations can interrupt the normal sequential flow of instruc~ion execution. For example, a wait state maybe imposed in a given machine cycle to provide more time for a memory or 110 device to communicate with the CPU. Wait states are needed when a fast microprocessor needs to communicate with a slow memory. Here's why:
Once the CPU addresses memory, it cannot proceed until the memory responds. While most memories respond faster than required, some cannot supply the addressed byte within the minimum time established by the CPU clock. Therefore, the memory must request a wait state when it receives the CPU signal that a memory read or write operation has commenced. After the memory responds, it signals the CPU to leave the wait state and continue processing.
Another situation that alters sequential instruc- tion execution is an interrupt. Interrupts actually improve CPU efficiency. For exam- ple, consider a computer that is processing a large volume of data, portions of which are to be output to a printer. The CPU can out- put to the printer in one machine cycle, but the printer may take many machine cycles to actually print the characters specified by the data byte, So, the CPU must remain idle until the printer can accept the next data byte from the CPU, or, if an interrupt capability is implemented, the CPU can output to the printer and then return to other data process- ing. When the printer is ready to accept the next data byte, it signals the CPU via special interrupt control line. When the CPU an- swers the interrupt it suspends main program execution and automatically switches to/the instructions that output to the printer, after which, the CPU continues .. with main pro- gram execution where processirig was suspended.
