ADC ADD WITH CARRY ADC
Encoding:
Memory or Register Operand with Register Operand:
10001 00 d w 1mod reg rIm 1
if d = 1 then LSRC = REG, RSRC = EA, DEST = REG else LSRC = EA, RSRC = REG, DEST = EA
Immediate Operand to Memory or Register Operand:
1100000 s w 1mod 0 1 0 rIm 1 data | Idata if s:w=01! |
LSRC = EA, RSRC = data, DEST = EA
Immediate Operand to Accumulator:
100 0 1 0 1 0 w 1 | data | 1 data if w=1 1 |
if w = 0 then LSRC = AL, RSRC = data, DEST = AL else LSRC = AX, RSRC = data, DEST = AX
ADC Operands | Clocks· | Transfers | Bytes | ADC Coding Examples |
register, register | 3 | - | 2 | ADCAX, SI |
register, memory | 9(13)+EA | 1 | AOC OX, BETA [SI] | |
memory, register | 16(24)+ EA | 2 | AOC ALPHA [BX] [SI], 01 | |
register, immediate | 4 | - | AOC BX, 256 | |
memory, immediate | 17(25) + EA | 2 | AOC GAMMA, 30H | |
accumulator, immediate | 4 | - | AOC AL, 5 |
*b(w): where b denotes the number of clock cycles for byte operands and w denotes the number of clock cycles for word operands.