Intel 210200-002 manual IAPX 88-BASED $100 BUS System

APPLICATION EXAMPLES

iAPX 88-BASED $100 BUS SYSTEM

One very popular standard for microcompu- ter systems is the S 100 Bus. This application example describes an S100 system which uses the iAPX 88 to implement a high perfor- mance system which has many other benefits.

First, an iAPX 88-based S100 system is easy to implement, because the CPU interface is very similar to the CPUs for which the standard SIOO was originally designed. For example, the hardware of an 8085-based S100 CPU c!lrd is very similar to this system.

Secondly, because this SIOO system is using an iAPX 88 CPU, standard SIOO memory, 1/0, peripherals, and other cards, can take advantage of the powerful iAPX 88 features to greatly enhance the capabilities of existing S 100 systems based on the 8080, Z80 or other 8-bit CPU's.

Another point is that, along with higher performance, the system also has the advant- age of the greatly relaxed iAPX 88 bus to accommodate slower memory, 1/0, and peripheral cards without the performance degradation of wait states.

The bus also directly supports the iAPX 88's 1 Megabyte memory address space.

As shown in the block diagram in Figure 4-6, the system has 3K bytes of EPROM (three 2708's), lK of ROM (two 2114s), fully buffered busses and demultiplexed address bus. The control and status busses have been decoded to provide compatible signals for the SIOO bus.

1/0, peripherals and additional memory are assumed to be on the other standard S100 cards in the system. A detailed schematic is shown in Figure 4-7.

iAPX 88-BASED CRT CONTROLLER

This application example describes an intel- ligent CRT controller based on the iAPX 88

and the 8276 Small System CRT controller. This design demonstrates the power of the iAPX 88 and LSI chips for a low component count.

A unique implementation shows how to eliminate the need for a DMA controller, while enabling the iAPX 88 to supply characters directly to the 8276 by means of interrupt-driven software.

The overhead on the processor is less than 30%, leaving it free to implement intelligent terminal functions, as local data processing.

The entire design requires only 22 IC packages.

The heart of the controller is an iAPX 88 operating at 5 MHz (Fig. 4-8). It is supported by two 8185 (1 K x 8) static RAMs, and a 2716 EPROM, containing control software. An 8251A programmable communication interface provides synchronous or asynchro- nous serial communications.

Baud rates are selected by switches on the board. The baud rate clock is generated by the 8253 programmable interval timer under software control.

An 8255A provides three 8-bit parallel 1/0 ports, two of which are utilized for keyboard scanning. The third port is .used to sense option switch settings and to sense the vertical retrace signal from the 8276 for CRT synchronization upon reset.

The CRT interface is controlled by an 8276 programmable CRT controller. The CRT dot and character timing is generated by an 8284A clock generator. A second counter of the 8253 dmer provides the appropriate horizontal retrace timing for the CRT monitor. A 2716 EPROM provides a user- programmable character generator.

A shift register transforms parallel data from the character EPROM into a serial bit stream

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