HARDWARE DESIGN

CLK

 

 

(see note 3)

(see note 4)

 

 

~--~~r------~s

PULSE 1

PULS.E..2

PULSE 3

 

MASTER RO

CPU GT

MASTER ITT

 

Master request is sampled by 8088

(see note 1)

Master grant is sampled by 8088

 

 

1.THE 8088 FLOATS S2, 51, So FROM 1.1.1 STATE ON THIS EDGE

2.THE 8088 FLOATS AxDx BUS,RD,AND LOCK ON THIS EDGE

3.THE OTHER MASTER FLOATS S2, 51, SO FROM 1.1.1 STATE ON THIS EDGE

4.THE OTHER MASTER FLOATS AxDx BUS, AND LOCK ON THIS EDGE

Figure 3-33. Request/Grant Sequence Timing (Maximum Mode Only)

3-28

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Intel 210200-002 manual Pulse PULS.E..2