Intel 210200-002 manual ==~Ta~~=J

ARCHITECTURE AND INSTRUCTIONS

TWO OPERAND FORMAT, SECOND OPERAND IS REGISTER

[ 001Ls~<[IIiu		OPCODE	10 I wi	I MOD I REG I RIM I
(optional)
[= --- 61SP-LO:=:=::J		[==~~-HI:==J
(optional)		(optional)
TWO OPERAND FORMAT, SECOND OPERAND ,IS CONSTANT
[001 I SEG I	Ii U	I 0 PCO DE	I S I w I	r-MI-:-:O-=-D"T"IO=-:P:""':C-=-O-=-DE=-II"::R""':":IM-:-11
(optional)	:==:1
[==DISP-LO		[== DISP~C=:=J		DATA-LO
(optional)		(optional)
[==~TA~~=::J
(optional)
ONE OPERAND FORMAT
.[001J)lG I110J		OPCODE	Iw I	I MOD IOPCODE I RIM I
(optional)
[==~SP-~	=J	[==61~-HI==J
(optional)		(optional)

FOR DEFINITION OF MOD AND RIM FIELDS, SEE FIGURE 2-5.

OTHER BIT FIELDS:

w= 0: 8-BIT OPERAND(S)

1:16-BIT OPERAND(S)

o = 0: DESTINATION IS FIRST OPERAN 0

1: DESTINATION IS SECOND OPERAND

S = 0: DATA = DATA HI, DATA LO			}	APPLIES IF
1: DATA = DATA-LO SIGN EXTENDED				W=1
					"
SEG:	SEGMENT REG			REGISTER
00	ES			a-BIT	16-BIT
01	CS	REG:		(W = 0)	(W= 1)
10	SS
11	OS	000		AL	AX
		001		CL	CX
		010		DL	OX
		011		BL	BX
		100		AH	SP
		101		CH	BP
		110		DH	SI
		111		BH	01

Figure 2-4. Defining Bits in Instructions with One and Two Operands

2-6