Intel 210200-002 manual External Interrupts

HARDWARE DESIGN

EXTERNAL INTERRUPTS

The 8088 has two inputs that may be used by external devices to signal interrupts, INTR and NMI.

The INTR (Interrupt Request) line is usually driven by an Intel® 8259A Programmable Interrupt Controller (PIC), which is in turn connected to the devices that need interrupt service. The 8259A is a very flexible compo- nent that is controlled by software com- mands from the iAPX 88. The PIC appears as a set of I/O ports to the software.

The 8259A's main job is to accept interrupt requests from the devices attached to it, determine which requesting device has high- est priority, then activate the iAPX 88 INTR line if the selected device has higher priority than the device currently being serviced (if any).

When INTR is active, the CPU takes different action depending on the state of the interrupt- enable flag (IF). No action takes place, however, until the currently executing instruc- tion has been completed. Some unusual cases are described under the heading of Interrupt Latency Exceptions. Then, if IF is clear - meaning that interrupts signaled on INTR are masked or disabled - the CPU ignores the interrupt request and processes the next instruction.

The INTR signal is not latched by the CPU, so it must be held active until a response is received or the request is withdrawn.

If interrupts on INTR are enabled (if IF is "1"), the CPU recognizes the interrupt request and processes it. Interrupt requests arriving on INTR can be enabled by executing an STI (set interrupt-enable flag) instruction, and disabled by the CLI (clear interrupt-enable flag) instruction. They also may be selectively masked (some types enabled, some disabled) by writing commands to the 8259A.

Note that to reduce the likelihood of exces- sive stack build-up, the STI and IRET instructions will reenable interrupts only after the end of the following instruction.

The CPU acknowledges the interrupt request by executing two consecutive interrupt acknow- ledge (INTA) machine cycles (Fig. 3-24). If a bus hold request arrives via the HOLD line during the INTA cycles, it is not honored until the INTA cycles have been completed. The first cycle signals the 8259A that the request has been honored.

During the second INTA cycle, the 8259A responds by placing a byte on the data bus. This byte represents the interrupt type (0-255) associated with the device requesting service.

	_1_ 2ND MACHINE CYCLE
T4	T1 I T2 I	T3
ClK
I	\		r
,-----_....II	\	I	)
	(	VECTOR
AD7-ADo--------------------------------------------	~	TYPE

Figure 3-24. Interupt Acknowledge Sequence

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