Intel 210200-002 manual 1L.~~

inter

iAPX 88/10

WAVEFORMS (Continued)

ASYNCHRONOUS		BUS LOCK SIGNAL TIMING
SIGNAL RECOGNITIO",!		(MAXIMUM MODE ONLy)
ClK\	-1\	Any eLK cycle---j	Any eLK Cycle -_I

NMI

INTR

I 1L.~~

I"gO,,::

ClK

NOTE: 1. SETlJP REQUIREMENTS FOR ASYNCHRONOUS

SIGNALS ONLY TO GUARANTEE RECOQNITION AT NEXT elK

REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

~

1

Previousgranl

A1AA,~~!: 1-,----------------1
Ao,-ADa	....
~~ ,I	----------------~	(SEE NOTE 1)

NOTE: 1. THE COPROCESSOR MAY NOT DRIVElHE BUSSES OUTSIDE THE REGION

•SHOWN WITHOUT InSKINO CONTENTION.

HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLy)

	'ClKCYCLE-	_.ri-'OR' CYCLES
_I _'HVCH • (SEE NO'E"
		,"1-,..~
CLK ~
HOlD~		1\ ----- + -- 1
		-TCLHAV
HLOA
....		TCLAZ
		COPROCESSOR

61 AFN-00826D