Intel 210200-002 manual Performance Measurements

APPENDIX

Zilog Z80

The Z80 is an eight bit N-channel MOS microprocessor currently available in two versions, the Z80A and Z80B. The maximum clock rates are 4 MHz for the Z80A and 6 MHz for the Z80B. Both speed selections- are used in benchmark timing.

The Z80 registers are grouped into the main, alternate and special purpose register sets. The main and alternate register sets are two identical sets of eight-bit registers. Each set consists of eight registers, one accumulator (A), one flag register (F), and six general purpose regis- ters: the B, C, D, E, H, and L. For some operations, the general purpose registers can be concatenated together into sixteen bit register pairs. The user can switch back and forth between the main and alternate register sets using the exchange instructions, but only one set can be active at anyone time. One exchange instruction (EX) allows the main accumulator and flags to be exchanged with the alternate accumulator and flags. The other ex- change (EXX) switches all of the general purpose registers at once. This is helpful for a single context switch, but makes it difficult to pass data between the main and alternate register sets.

The Z80 has six special purpose registers: IX, IY, IP, SP, R, and I. The IX and IY are sixteen bit index regis- ters which can be added to a displacement to provide indexed addressing. The instruction pointer (lP) and stack pointer (SP) are also sixteen bit registers. The R register is a seven bit counter used for dynamic RAM refresh. The I register is a page register which contains the upper eight address bits for a Mode 2 interrupt.

The Z80 supports one nonmaskable interrupt and has three modes for maskable interrupts. In Mode 0, the Z80 requires the interrupting device to place one instruc- tion on the data bus. (This mode is identical to the way the 8080 handles interrupts.) Mode 1 performs an automatic restart to location 038H. In Mode 2, the in- terrupting device places an eight bit address on the bus. These eight bits are concatenated with the interrupt page register to point to a location in a memory based table of interrupt vectors.

The basic bus timing of the Z80 consists of an opcode fetch (Ml), a memory read (M2), and a memory write (M3). During the Ml cycle, the CPU first fetches and then decodes the instruction opcode. (Because the Z80 does not have a queue there is no overlap of opcode fetch and execution.) The Z80 then outputs a memory refresh address. If no wait states are used, Ml is four clock cycles, while M2 and M3 are each three clock cycles. The Ml zero wait state memory access times are 250 ns and 140 ns for the Z80A and Z80B. These times can be increased by adding wait states. Each wait state adds one clock per memory reference. This adds 250 ns and 165 ns per bus cycle to the Z80A and Z80B to give access times of 500 ns and 305 ns respectively.

The instruction set of the Z80 contains eight major groups: Load and Exchange, Arithmetic, Logical, Rotate and Shift, Bit Manipulation, I/O, CPU and pro- gram control, and Block instructions. The processor operates on bits, BCD digits, eight-bit bytes and sixteen- bit words. The Block instructions will search or transfer a block of memory using the DE and HL registers as pointers and the BC register as a counter.

The Z80 provides seven addressing modes to access data operands. It allows the use of eight or sixteen bit im- mediate addresses, indexing using the IX or IY with an eight bit displacement and register indirect addressing using register pairs.

PERFORMANCE MEASUREMENTS

The processors were compared in four categories of per- formance measurements. The first two categories measure the execution speed of the iAPX 88/10 and the Z80. The next comparison looks at the ease of use which is the number of lines of code in each program. The last basis for comparison is memory use or coding effi- ciency.

The first performance measurement tests the processors for maximum execution speed. This is important for many applications where high throughput is a critical factor. To measure this, the processors were run at max- imum speed with no wait states. The maximum clock rates are 5 MHz for the iAPX 88/10, 4 MHz for the Z80A and 6 MHz for the Z80B. Table 2 gives the results of this measurement for the iAPX 88/10 and the Z80A. Table 3 gives the results for the iAPX 88/10 and the Z80B.

The next measurement again examines execution speed, but this time memory address access time was also con- sidered. While the processors were again run at their maximum clock rates, they were also required to be compatible with slow memories. The Z80B has a memory access time of 140 ns which often requires the use of expensive speed selected memories. And there are no EPROMs which could be used in this system without wait states. Because of this, many Z80B systems will be required to run with one, or even two wait states, pro- viding memory access times of 305 ns and 470 ns. Many systems using the Z80A also require one wait state which increases the memory access time from 250 ns to 500 ns. The iAPX 88 has a zero wait state memory ac- cess time of 460 ns. This is relaxed enough to allow the use of ordinary nonspeed selected memories including most EPROMs. Tables 4 and 5 compare the execution speeds of the processors for systems which have the re- quirement of a relaxed memory access time. The iAPX 88 is run with no wait states because of its 460 ns zero wait state timing. The Z80A is measured with one wait state providing a 500 ns memory access time. The Z80B is measured for both the one and two wait state cases. These measurements give relative performance for relaxed memory access time.

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