Intel 210200-002 manual Hold 101M

HARDWARE DESIGN

Because the 2114 is a lK x 4 memory, we need two 2114's to make an 8-bit wide memory. The two 2114s are connected to the data bus so that one drives data lines 00-03, and the other drives 04-07. Any read or write to the 2114s will enable both chips at the same time to move the 8-bit data byte.

The chip select input cannot be connected directly to the output of the address decoder, as was done with the 2716, because the 2114 has no output enable pin. Instead, CS is delayed by ORing the chip select with the DEN output of the 8088. This delays the 2114s from outputting the data until after the address has been latched by the falling edge of ALE and the 8088 has tri-stated its address/ data bus.

LARGE DE-MULTIPLEXED BUS SYSTEMS

The bus configuration in Figure 3-10 is fine for medium-sized systems, but if too many components are connected to the busses, the 8088's outputs will not be able to drive the system.

Figure 3-5 shows a system where 8282 latches have been added to lines As-AI5 and AI6-AI9, and an 8286 octal transceiver has been added to the multiplexed data bus. This accomplishes two things.

First, address bits A16-A19 are multiplexed with status bits S3-S6 and therefore must be latched like lines ADo-AD7 if they are to be used in addressing.

Second, the 8286 on the data bus, and the 8282s on the address bus, can drive much higher loads than the 8088 can. With the 8088

ALE

STB

A19-

8282

1

A16-A19

A16

A1S-

STB

8282

I

A8-A1S

8088

A8

D

CPU

STB

Vcc

r

1

AD7-

8282

1

AO-A7

y

8284A

ADO

0.

CLOCK ~ ClK

I

I

GENERATOR r- READY

I

;- RES

I-+- RESET

8286.1

DO-D7

I

RDY

T OEI

+

INTA

DT/R

r

GND

INTR

DEN

, . - HOLD 101M

-

-

.---

HlDA

RD

-

-

rNMI

WR

r

r

r

-

-

-

-

T'ST

•

•

•

1<-

WRRDCS

J.IWRRDCE

WR RDCS

DATA

INTR

PERIPHERAL

I/"--

HlDA

If

MEMORY

HOLD

INTR INTA

ADDRESS

t

Figure 3-11. iAPX 88 with Buffered Demultiplexed Busses

3-12