Intel 210200-002 manual 11000011 w 1mod reg rIm, 001 0 reg

XCHG

EXCHANGE XCHG

Encoding:

Memory or Register Operand with Register Operand:

11000011 w 1mod reg rIm 1

SRC = EA, DEST = REG

Register Operand with Accumulator:

1 1 001 0 reg 1

SRC = REG, DEST = AX

XCHG Operands	Clocks*	Transfers	Bytes	XCHG Coding Example
accumulator, reg16	3	-	1	XCHG AX, BX
memory, register	17(25) + EA	2	2-4	XCHG SEMAPHORE, AX
register, register	4	-	2	XCHG AL, BL

*b(w): where b denotes the number of clock cycles for byte operands and w denotes the number of clock cycles for word operands.

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