Intel 210200-002 manual Application Examples

APPLICATION EXAMPLES

I/O intensive tasks, such as DMA, are handled by the 8089 I/O Processor. This configuration is said to use the lOP in local mode because the 8088 and the 8089 share all the system resources and the common local bus. The system name for the 8088/8089 combination is iAPX 88/ 11.

Use of the system resources is arbitrated by the Request/ Grant (RQ/ GT) line which serves the same function as HOLD/HLDA in minimum mode. This enables the 8089 to gain control of the system to read parameter blocks from memory, perform DMA, or execute other I/O processing tasks.

Figure 4-11 is a block diagram of an iAPX 88/21 system. Here the 10 processor is said to be in remote mode because it has its own local resources separate from those of the 8088.

The processors communicate with each other and can share resources via the MULTIBUS™ system bus. Control of the MULTIBUS™ is handled by the 8289 Bus Arbiter. Note that each subsystem has its own 8289 to access the system bus in order to use shared resources and communicate with the other subsystem.

An example of one possible configuration for the 8089 in Remote Mode is shown in Figure 4-13. This subsystem has its own local I/O and memory resources. For many systems of this type, a large percentage of the 8089's tasks will use its local resources and not require use of the multimaster system bus.

But, when the 8089 does need to use shared resources, the 8289 will obtain control of the

system bus for the 8089. The 8289s in the system will assure that bus contention and deadlock do not occur.

Some systems will have several separate data processing tasks which can all be operated on at the Bame time. This could use a con- figuration such as Figure 4-14, which has two iAPX 88/ 10 subsystems and one iAPX 86/ 10 subsystem. This could easily be expanded by adding' Numeric Data Processors (iAPX 88/20) 8089 I/O Processors, and/or more iAPX 88, 86 subsystems. Each subsystem has its own local bus on which it can attach its own resources.

In this system, the LOCK output of the processors can be very important. When one subsystem begins an operation such as a read- modify-write using a shar<::d resource, the CPU can use the LOCK to assure that the operation is completed before another sub- system can take control of the system bus.

The LOCK signal tells the 8288 and 8289 that control of the bus must not be given up between the two bus cycles of this type of instruction. In this way, an exchange instruct- ion can be used to set a semaphore flag without the possibility of losing the bus between the read and write cycles of the exchange.

The iAPX 88 architecture promotes modular mUltiprocessing designs. The maximum mode interface with the 8288 Bus Controller and 8289 Bus Arbiter provide all the signals necessary for implementing multimaster busses and greatly simplifying the design of large systems.

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