Intel 210200-002 manual 1100001 0 w 1mod reg rIm, 11111 011 w 1 mod 000 rIm 1 data

TEST

TESTTEST

Encoding:

Memory or Register Operand with Register Operand:

1100001 0 w 1mod reg rIm 1

LSRC = REG, RSRC = EA

Immediate Operand with Memory or Register Operand:

11111 011 w 1mod 000 rIm 1 data data if w=1

LSRC = EA, RSRC = data

Immediate Operand with Accumulator:

11 0 1 0 1 0 0 w 1 data		1 data if w=1
if w = 0 then LSRC = AL, RSRC = data
else LSRC = AX, RSRC = data
TEST Operands	Clocks*		Transfers	Bytes	TEST Coding Example
register, register		3	-	2	TEST SI, DI
register, memory	9(13) + EA		1	2-4	TEST SI, END~COUNT
accumulator, immediate		4	-	2-3	TEST AL, 00100000B
register, immediate		5	-	3-4	TEST BX, OCC4H
memory, immediate	11(15)+EA		1	3-6	TEST RETURN_CODE, 01 H

*b(w): where b denotes the number of clock cycles for byte operands and w denotes the number of clock cycles for word operands.

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