Intel 210200-002 manual +- Reset

HARDWARE DESIGN

This signal floats to 3-state OFF during "hold acknowledge" (Fig. 3-5).

INTR. Interrupt Request is a level-triggered active HIGH input, sampled during the last clock cycle of each instruction. It tells the 8088 to stop what it is currently doing and service an 110 or peripheral device.

When INTR is detected HIGH, the 8088 jumps to an interrupt service routine via an interrupt vector table in system memory.

INTR can be internally masked through software by resetting the interrupt enable bit in the Flag register. INTR is internally synchronized.

INTA. Used as a read strobe during interrupt acknowledge cycles, INTA is active· LOW during T2, T3, and T4 of each interrupt acknowledge cycle. INTA is never floated.

880.This is a status output. When decoded with IO I M and D RI R, SSO specifies the type of bus activity in progress (Fig.3-6).

IO/iiii	OT/R	550
1(HIGH)	0	0	Interrupt Acknowledge
1	0	1	Read 1/0 port
1	1	0	Write 1/0 port
1	1	1	Halt
O(lOW)	0	0	Code access
0	0	1	Read memory
0	1	0	Write memory
0	1	1	Passive

Figure 3-6. iAPX 88 Status Decoding

					ALE	STB
					A19-	8282	I			A16-A19
					A16
					A15-	STB					)
				8088		8282	I			A8-A15
	D				A8
				CPU		STB
Vec	r	1			AD7-	8282	I			AO-A7	-n
I	8284A			I-+- ClK	ADO					I
	CLOCK							I
GENERATOR I-+-READY							I
~ RES				I-+- RESET		8286·1				00-07
I	ROY					T OEI		A	A		A
	+			INTA DT/A"		• r
GND				INTR	DEN						-
			~ HOLD		101M
			-	HLDA	RD				,I	,I	-
											-
				,.. NMI TEST		" I
											-
					WR
						WRRDCS			J.IWRRDCE	WR RDCS	I<=-
									If	MEMORY
						HLDA				DATA
						INTR		PERIPHERAL		ADDRESS 1<==
						HOLD			INTR INTA
									t

Figure 3-5. iAPX 88 with Buffered Demultiplexed Busses

3-5