iAPX 88/10
A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
SymbolParameter
TClCl ClK Cycle Period
TClCH ClK low Time
TCHCl ClK High Time
TCH1CH2 ClK Rise Time
TCl2Cl1 ClK Fall Time
TDVCl Data In Setup Time
TClDX Data In Hold Time
RDY Setup Time into 8284
TR1VCl
(See Notes 1, 2)
RDY Hold Time into 8284
TClR1X
(See Notes 1, 2)
8088 |
| 8088·2 |
|
|
|
Min. | Max. | Min. | Max. | Units | Test Conditions |
200 | 500 | 125 | 500 | ns |
|
118 |
| 68 |
| ns |
|
69 |
| 44 |
| ns |
|
| 10 |
| 10 | ns | From 1.0V to 3.5V |
| 10 |
| 10 | ns | From 3.5V to 1.0V |
30 |
| 20 |
| ns |
|
10 |
| 10 |
| ns |
|
35 |
| 35 |
| ns |
|
a |
| a |
| ns |
|
TRYHCH
READY Setup Time into
118 | 68 | ns |
8088
TCHRYX READY Hold Time into 8088
30 | 20 | ns |
TRYlCl
READY Inactive to ClK (See
ns |
Note 4)
Setup Time for Recognition
TINVCH (INTR, NMI, TEST) (See Note 2)
30 | 15 | ns |
TGVCH | RQ/GT Setup Time | 30 | 15 |
TCHGX | RQ Hold Time into 8086 | 40 | 30 |
TILIH | Input Rise Time |
| 20 |
(Except ClK) |
| ||
|
|
| |
TIHll | Input Fall Time (Except ClK) |
| 12 |
NOTES:
1.Signal at 8284 or 8288 shown for reference only.
2.Setup requirement for asynchronous signal only to guarantee recognition at next elK.
3.Applies only to T2 state (8 ns into T3 state).
4.Applies only to T2 state (8 ns into T3 state).
57
ns ns
20 ns From 0.8V to 2.0V
12 ns From 2.0V to 0.8V
