iAPX 88/10
Table 1. Pin Description (Continued)
The following pin function descriptions are for the 8088, 8228 system in maximum mode (i.e., MNIMX=GND.) Only the pin functions which are unique to maximum mode are described; all other pin functions are as described above.
Symbol | Pin No. | Type | Name and Function |
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82,81,80 | o | Status: is active during clock high of T4, T1, |
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| and T2, and is returned to the passive state. |
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| (1,1,1) during T3 or during Tw when READY is |
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| HIGH. This status is used by the B2BB bus con- |
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| troller to generate all memory and I/O access |
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| control signals. Any change by 82, 81, or SO | S2 | S1 | ", | CHARACTERISTICS |
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| during T4 is used to indicate the beginning of a | o(LOW) | , | Interrupt Acknowledge | |
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| , | , | 1 | Read 110 pori | |
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| bus cycle, and the return to the passive state in | , | 1 | , | ::~e~oport |
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| , | 1 | 1 |
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| T3 or Tw is used to indicate the end of a bus | ~ (HIGH) | , | , | CodeacceS$ |
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| , | 1 | , | Write memory | |
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| cycle. |
| , | 1 | Aead"!amory |
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| 1 | 1 | , | Pa'$ive | |
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| These signals float to |
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| acknowledge". During the first clock cycle after |
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| RESET becomes active, these signals are active |
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| HIGH. After this first clock, they float to 3·state |
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| OFF. |
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RQ/GTO, | 30,31 | I/O | Request/Grant: pins are used by other local bus masters to force the processor | ||||
RQ/GT1 |
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| to release the local bus at the end of the processor'scurrent bus cycle. Each pin | ||||
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| is bidirectional with RQ/GTO having higher priority than RQ/GT1. RQ/GT has an | ||||
internal
1.A pulse of one CLK wide from another local bus master indicates a local bus request ("hold") to the BOBB (pulse 1).
2.During a T4 or TI clock cycle, a pulse one clock wide from the BOBB to the requesting master (pulse 2), indicates that the BOBB has allowed the local bus to float and that it will enter the "hold acknowledge" state at the next CLK. The CPU'sbus interface unit is disconnected logically from the local bus during "hold acknowledge". The same rules as for HOLD/HOLDAapply as for when the bus is released.
3.A pulse one CLK wide from the requesting master indicates to the BOBB (pulse 3) that the "hold" request is about to end and that the BOBB can
Each
There must be one idle CLK cycle after each bus exchange. Pulses are active
LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met:
1.Request occurs on or before T2.
2.Current cycle is not the low bit of a word.
3.Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4.A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1.Local bus will be released during the next clock.
2.A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.
40 | AFN·00826D |
