iAPX 88/10
External Synchronization via TEST
As an alternative to interrupts, the 8088 provides a single
a byte of information is read from the data bus, as sup- plied by the interrupt system logic (i.e. 8259A priority in- terrupt controller). This byte identifies the source (type) of the interrupt. It is multiplied by four and used as a pointer into the interrupt vector lookup table, as .de- scribed earlier.
If a local bus request occurs during WAIT execution, the 8088
Basic System Timing
In minimum mode, the MN/MX pin is strapped to Vee and the processor emits bus control signals compatible with the 8085 bus structure. In maximum mode, the MN/MX pin is strapped to GND and the processor emits coded status information which the 8288 bus controller uses to generate MULTIBUS compatible bus control signals.
System Timing - Minimum System
(See Figure 8,)
The read cycle begins in T1 with the assertion of the ad- dress latch enable (ALE) signal. The trailing (low gOing) edge of this signal is used to latch the address informa· tion, which is valid on the address/data bus
A write cycle also begins with the assertion of ALE and the emission of the address. The 101M Signal is again asserted to indicate a memory or 110 write operation. In T2, immediately following the address emission, the processor em its the data to be written into the ad- dressed location. This data remains valid until at least the middle of T4. During T2, T3, and Tw, the processor asserts tile write control signal. The write (WR) signal becomes active at the beginning of T2, as opposed to the read, which is delayed somewhat into T2 to provide time for the bus to float.
The basic dilference between the interrupt acknowl- edge cycle Clnd a read cycle is that the interrupt acknowledge (INTA) signal is asserted in place of the read (RD) signal and the address bus is floated. (See Figure 9.l.ln the second of two successive INTA cycles,
Bus Timing - Medium Complexity Systems
(See Figure 10J
For medium complexity systems, the MN/MX pin is con- nected to GND and the 8288 bus controller is added to the system, as well as an 8282/8283 latch for latching the system address, and an 8286/8287 transceiver to allow for bus loading greater than the 8088 is capable of handling. Signals ALE, DEN, and DT/R are generated by the 8288 instead of the processor in this configuration, although their timing remains relatively the same. The 8088 status outputs (52, S1, and SO) provide type of cycle information and become 8288 inputs. This bus cycle information specifies read (code, data, or 110), write (data or 110), interrupt acknowledge, or software halt. The 8288 thus issues control Signals specifying memory read or write, 110 read or write, or interrupt acknowledge. The 8288 provides two types of write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. The 8286/8287 trans- ceiver receives the usual T and DE inputs from the 8288'sDT/R and DEN outputs.
The pOinter into the interrupt vector table, which is passed during the second INTA cycle, can derive from an 8259A located on either the local bus or the system bus. If the master 8289A priority interrupt controller is positioned on the local bus, a TTL gate is required to disable the 8286/8287 transceiver when reading from the master 8259A during the interrupt acknowledge se- quence and software "poll".
The 8088 Compared to the 8086
The 8088 CPU is an
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