Intel 210200-002 manual ~Atui

HARDWARE DESIGN

Conveniently, most. Intel peripherals, EPROMs and RAMs in the iAPX 88 family provide output enable or read inputs which prevent this from happening.

Observe how some memory and peripheral components are connected in this system configuration. A 2716 2K x 8 EPROM and two 2114 RAMs are connected in an iAPX 88 system with a demultiplexed address bus (Fig. 3-10). Address lines Ao-A10from the demultiplexed address bus are connected to the address inputs Ao-AlO of the 2716.

The multiplexed data bus is connected to the data output of the 2716. The CE (chip ena- ble) input is driven from an address decoder. This could be either a decoder PROM or a TIL decoder such as a 74LS139.

Another possibility is to use a linear chip select, described previously.

The output enable (OE) of the 2716 is driven by the 8088's RD control line. This enables the output data onto the data bus from the 2716 with the proper timing to prevent bus contention problems.

The connections for a 2114 RAM are a little different from a 2716 because the 2114 is a lK x 4 memory, and because it can be written-to as well as read. Also, because it does not have an output enable, care must be taken to not cause bus contention by driving the data bus too early.

.The address pins of the 2114 are directly con- nected to AO-A9 on the de-multiplexed address bus. The data pins 1/01-1/04are connected to the multiplexed data bus.

A19-			A16-A19					~
A16
A15-			AS-A15
AS
	k:	ro -
ADD		, - STB
AD7-		8282	AD-A7
ALE -		~
8088			00-07
CPU
RD -		r	T	r-			r-	;==!
WR -				r-			I -
	-	~Atui	,llr			WE
DEN						I
		2716~	2114			2114 ADD~ESS
		00-'57 OE AO-A10	WEOD AO-A9
			T-	00-03	04~		DECyDER
		CL-				CS1
						l~

I

Figure 3-10. Oemultiplexed Bus Connections

3-11