Intel 210200-002 manual IntJ8284A

intJ8284A

Table 1. Pin Description

Symbol	'i'Vpa		Name and Function
AEN1,	I	Address Enable: AEN is an active LOW
AEN2		signal. AEN serves to qualify its respective
		Bus Ready Signal (RDYI or RDY2). AENI
		validates RDYI while AEN2 validates RDY2.
		Two AEN signal inputs are useful in system
		configurations which permit the processor to
		access two Multi-Master System Busses. In
		non Multi-Master configurations the AEN
		signal inputs are tied true (LOW).
RDY1,	I	Bus Ready: (Transfer Complete). RDY is an
RDY2		active HIGH signal which is an indication from
		a device located on the system data bus that
		data has been received, or is available. RDYI
		is qualified by AEN'i while RDY2 is qualified
		by AEN2.
ASYNC	I	Ready Synchronization Select: ASYNC is an
		input which defines the synchronization
		mode of the READY logic. When ASYNC is
		low, two stages of READY synchronization are
		provided. When ASYNC is left open or HIGH a
		single stage of READY synchronization is
		provided.
READY	0	Ready: READY is an active HIGH signal
		which is the synchronized RDY signal input.
		READY is cleared after the guaranteed hold
		time to the processor has been met.
XI, X2	I	Crystal In : XI and X2 are the pins to which a
		crystal is attached. The crystal frequency is 3
		times the desired processor clock frequency.
F/C	I	FrequencylCrystal Select: F/C is Ii strapping
		option. When strapped LOW, FIC permits ihe
		processor's.!:!ock to be generated by the crys-
		tal. When F/C is strapped HIGH, CLK is gener-
		ated from the EFI input.
EFI	I	External Frequency: When F/C is strapped
		HIGH, CLK is generated from the input fre-
		quency appearing on this pin. The input

signal is a square wave 3 times the frequency of the desired CLK output.

FUNCTIONAL DESCRIPTION

General

The 8284A is a single chip clock generatorldriver for the iAPX 86, 88 processors. The chip contains a crystal- controlled oscillator, a divide·by·three counter, com· plete MULTIBUSTM "Ready" synchronization and reset logic. Refer to Figure 1 for Block Diagram and Figure 2 for Pin Configuration.

Oscillator

The oscillator circuit of the 8284A is designed primarily for use with an external series resonant, fundamental mode, crystal from which the basic operating frequency is derived.

Symbol	'i'Vpe		Name and Function
CLK	0 Processor Clock: CLK is the clock output
		used by the processor and all devices which
		directly connect to the processor'slocal bus
		(i.e., the bipolar support chips and other MOS
		devices). CLK has an output frequency which
		is '13ofthe crystal or EFI input frequency and a
		'13 duty cycle. An output HIGH of 4.5 volts
		(Vcc= 5V) is provided on this pin to drive MOS
		devices.
PCLK	0	Peripheral Clock: PCLK is a TIL level pe-
		ripheral clock signal whose output frequency
		is V. that of CLK and has a 50"A. duty cycle.
OSC	0	Oscillator Output: OSC is the TIL level out-
		put of the internal oscillator circuitry. Its fre-
		quency is equal to that of the crystal.
RES	I	Reset In: RES is an active LOW signal which
		is used to generate RESET. The 8284A
		provides a Schmitt trigger input so that an RC
		connection can be used to establish the
		power-up reset of proper duration.
RESET	0	Reset: RESET isan active HIGH signal which
		is used to resetthe 8086 family processors. Its
		timing characteristics are determined by
		RES.
CSYNC	I	Clock Synchronization: CSYNC is an active
		HIGH signal which allows multiple 8284As to
		be synchronized to provide clocks that are in
		phase. When CSYNC is HIGH the internal
		counters are reset. When CSYNC goes LOW
		the internal counters are allowed to resume
		counting. CSYNC needs to be externally syn-
		chronized to EFI. When using the internal os-
		cillator CSYNC should be hardwired to
		ground.
GND		Ground.
Vcc		Power:	+5V supply.

The crystal frequency should be selected at three times the required CPU clock. XI .and X2 are the two crystal input crystal connections. For the most stable operation of the oscillator (OSC) output circuit, two series resistors (R1 = R2 = 5100) as shown in the waveform figures are recommended. The output olthe oscillator is buffered and brought out on OSC so that other system timing signals can be derived from this stable, crystal-controlled source.

For systems which have a VCC ramp time"" tV/ms andlor have inherent board capacitance between XI or X2, ex- ceeding 10pF (not including 8284A pin capacitance), the configuration in Figures 4 and 6 is recommended. This circuit provides optimum stabilityforthe oscillatorin such extreme conditions. It is advisable to limit stray ca- pacitances to less than 10pF on XI and X2 to minimize deviation from operating at the fundamental frequency.

65 AFN·01472B