Intel 210200-002 manual Internal Interrupts

HARDWARE DESIGN

The type assignment is made when the 8259A is initialized by software in the iAPX 88.

The CPU reads this type code, locates the corresponding interrupt vector in the inter- rupt vector table, and calls the corresponding interrupt procedure.

Interrupt Latency Exceptions.

There are a few cases in which an interrupt request is not recognize~ until after the fol- I

lowing instructioll. Repeat, LOCK, and segment override prefixes are considered "part of' the instructions they prefix; no interrupt is recognized between execution of a prefix and an instruction.

AMOV (move) to segment register instruc- tion and a POP segment register instruction are treated similarly: no interrupt is recog- nized until after the following instruction.

This mechanism protects a program that is changing to a new stack by updating SS and SP. If an interrupt were recognized after SS has been changed, but before SP has been altered, the processor would push the flags, CS, and IP into the wrong area of memory.

Therefore, whenever a segment register and another value must be updated together, the segment register should be changed first, fol- lowed immediately by the instruction that changes the other value.

WAIT and repeated string instruction are 2 cases where an interrupt request is recognized in the middle of an instruction. In these cases, interrupts are processed after any completed primitive operation or wait test cycle.

Externat Interrupt

An external interrupt request may also arive on another CPU input, NMI (non-maskable interrupt). This line is edge-triggered(INTR is level-triggered) and must be active for at least two clock cycles. It is generally used to signal the CPU of a "catastrophic" event, such as imminent loss of power, memory error, or bus parity error.

Interrupt requests arriving on NMI cannot be disabled. They are latched by the CPU, and have higher priority than an interrupt request on INTR.

If an interrupt request arrives on both lines during instruction execution, NMI will be recognized first. Non-maskable interrupts are pre-defined as type 2, which means that the address of the service routine will be found in the interrupt vector table at memory location 8 (Fig. 3-25). Because NMI is predefined as type 2, the processor does not need to be supplied with a type code to call the NMI procedure.

Interrupt Latency

The time required for the CPU to recognize an external interrupt request depends on how many clock periods remain in the execution of the current instruction. The longest latency occurs when a multiplication, division, variable- bit shift or rotate instruction is executing when interrupt request arrives.

As mentioned previously, in a few cases, worst-case latency will span two instructions rather than one.

INTERNAL INTERRUPTS

An INT instruction generates an interrupt immediately upon completion of its execu- tion. The interrupt type, coded into the instruction, lets the CPU obtain the interrupt routine address from the interrupt vector table.

Since any type code may be specified, soft- ware interrupts may be used to test interrupt proced ures written to service external devices.

The CPU itself generates a type 0 interrupt immediately following execution of a DIV or IDIV (divide, integer divide) instruction, if the calculated quotient is larger than the spec- ified destination.

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