Intel 210200-002 manual Characteristics

intJ8284A

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES

Symbol	Parameter
tCLCL	CLK Cycle Period
tCHCL	CLK HIGH Time
tCLCH	CLK LOW Time
tCH1CH2	CLK Rise or Fall Time
tCL2CLl
tpHPL	PCLK HIGH Time
tpLPH	PCLK LOW Time
tRYLCL	Ready Inactive to CLK (See Note 4)
tRYHCH	Ready Active to CLK (See Note 3)

Min.	Max.	Units	Test Conditions
100		ns
('13 tCLcd+2 for CLK Freq. ,,;; 8 MHz		ns	Fig. 7 & Fig. 8
(Y3 tCLcd+6 for CLK Freq.=10 MHz
(% tCLcd-15 for CLK Freq.,,;;8 MHz		ns	Fig. 7 & Fig. 8
(% tCLcL)-14 for CLK Freq.=10 MHz
	10	ns	1.0V to 3.5V
tCLCL-20		ns
tCLCL-20		ns
-8		ns	Fig. 9 & Fig. 10
(% tCLcd-15 for CLK Freq.,,;;8 MHz		ns	Fig. 9 & Fig. 10
(% tCLcd-14 for CLK Freq.=10 MHz

tCLIL	CLK to Reset Delay		40	ns
tCLPH	CLK to PCLK HIGH DELAY		22	ns
tCLPL	CLK to PCLK LOW Delay		22	ns
tOLCH	OSC to CLK HIGH Delay	-5	22	ns
tOLCL	OSC to CLK LOW Delay	2	35	ns
tOLOH	Output Rise Time (except CLK)		20	ns	From O.BV to 2.OV
IoHoL	Output Fall Time (except eLK)		12	ns	From 2.OV to 0.8V

NOTES:

1.,,= EFI rise (5 ns max) + EFI fall (5 ns max).

2.Setup and hold necessary only to guarantee recognition at next clock.

3.Applies only to T3 and TW states.

4.Applies only to T2 states.

A.C. TESTING INPUT, OUTPUT WAVEFORM

INPUT/OUTPUT

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FORA LOGIC "I" AND 0.45V FOR A LOGIC "D." TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A LOGIC "I" AND "D."

A.C. TESTING LOAD CIRCUIT

"'T'"VL: '.oav

RJ. = 32sn

DEVICE

UNDER I --

TEST

r CL

CL : l00pF FOR CLK

CL: 30pF FOR READY

68 AFN'()1472B