Intel 210200-002 manual List of Figures

List of Figures (cont.)

CHAPTER 3			Page
3-1	8088 CPU Pins		3-1
3-2	Time Multiplexing of Address and Data	......................................	3-2
3-3	Decoding of Status Signals S3-S6		3-2
3-4	iAPX 88 Multiplexed Bus System		3-4
3-5	iAPX 88 With Buffered Demultiplexed Busses		3-5
3-6	iAPX 88 Status Decoding	. . . .. . ... . .. . .. . . . . . .. . . . . . . .... .. . . . . ..	3-5
3-7	iAPX 88 Basic Machine Cycle		3-7
3-8	iAPX 88 Compatible Multiplexed Bus Components		3-8
3-9	Multiplexed Bus Connections		3-10
3-10	DemultiplexedBusConnections		3-11
3-11	iAPX 88 With Buffered Demultiplexed Busses		3-12
3-12	How 16-bit Data is Arranged in 8-bit Memory		3-13
3-13	Generating Clock Signal With 8284A		3-13
3-14	CPU State Following Reset		3-14
3-15	iAPX 88 Bus Condition During Reset		3-15
3-16	iAPX 88 Bus During Reset		3-15
3-17	8284A Reset Circuit	•	3-16
3-18	Constant Current on Reset Circuit		3-16
3-19	Normally READY Wait State Timing		3-17
3-20	Normally Not READY Wait State Timing		3-18
3-21	Using ROY 1/RDY 2 to Generate READy		3-19
3-22	Using AEN1/AEN2 to Generate READY		3-19
3-23	Single Wait State Generator		3-19
3-24	Interrupt Acknowledge Sequence		3-20
3-25	Interrupt Vector Table in Memory		3-21
3-26	Interrupt Priorities		3-23
3-27	iAPX 88 Bus Condition During HOLD	.......................................	3-24
3-28	iAPX 88 and 8237A Connections		3-25
3-29	HOLD/HLDA Timing		3-26
3-30	iAPX 88 Using Maximum Mode		3-26
3-31	Min.lMax. Mode Pin Assignments		3-27
3-32	Queue Status Decoding	.. . . . . . . .. . . . . . . . . . . .. . . .. . . . . . . .. . . . ..	3-27
3-33	Request Grant Sequence Time (Max. Mode Only)		3-28
3-34	iAPX 88/21 Configuration		3-29
CHAPTER 4
4-0	iAPX 88 Multiplexed System Design Example		4-2
4-1	iAPX 88 Demo Board Address Map		4-4
4-2	Vest Pocket Computer Component Layout		4-5
4-3	Vest Pocket Schematic		4-6
4-4	iAPX 88 Demultiplexed Bus System		4-8
4-5	2114 Chip Select Connection		4-11
4-6 iAPX 88 S100 Bus System			4-11
4-7	iAPX 88 S100 Schematic		4-12
4-8	CRT Controller Block Diagram		4-15
4-9	8276 Row Buffer Loading		4-16
4-10	Escape Character Recognition Code		4-17
4-11	iAPX 88 Multiprocessing System		4-18
4-12	Typical iAPX 88 Local Mode Configuration		4-19
4-13	Typical 8089 Remote Mode Configuration		4-21
4-14	iAPX 86,88 Multiprocessing System		4-22

(continued)

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