Tektronix 071-0590-00 user manual Bert Clock, Output Amplifiers, Data Coding, NRZ

BERT Primer

BERT Clock

A clock source is necessary to provide the timing for generation of the BERT digital output, and to provide the logic strobe for acquisition of the data by the receiver. The Clock must provide clean, sharp logic transitions and needs to be delayable to account for time the signals from the BERT take to propagate through the DUT. Most BERTs have an internal clock source. All BERTs have the ability to operate using an External Clock. Some BERTs have the ability to derive the internal clock using an External Reference signal at a fixed frequency, usually 10 MHz, as a basis for increased stability and frequency accuracy. Providing External Clock allows the possibility of modulating clock frequency (adding jitter) in order to stress ability of clock recovery circuit in DUT to withstand conditions of noise and pulse dispersion typically found in data transmission systems and circuits.

Output Amplifiers

BERT Output Amplifiers are responsible for providing features such as amplitude offset, peak-to-peak levels, impedances and the degree to which these may be set and varied for the purpose of accommodating the DUT, or testing sensitivity levels of the DUT. These amplifiers also determine or limit the availability of single-ended or differential output. The typical electrical I/O on our BERTs is a 1-volt signal centered around ground, either Differential or Single-Ended. Differential outputs provide an inverted “copy” of the output signal and are used to drive complimentary inputs. If a single-ended signal is needed, the complimentary output should always be terminated to the appropriate load to insure best signal quality.

Data Coding, NRZ

Data generated by a BERT is defined according to certain standard voltage levels, amplitude swings and transitions which the BERT Receiver will understand as representing a logical “1” or “0”. The most common type of encoding is “NRZ” (non-return to zero). For NRZ encoding, consecutive 1’s, for example, cause the output level to hold at the “true” state, rather than changing between consecutive bits. The level for NRZ only changes when there is a transition from 1 to 0, or 0 to 1. Other coding schemes are: RZ (return to zero), CMI, AMI... and many others. Coding schemes may be optimized to make it easier to recover clock at the far end, or to attempt to keep voltage levels balanced on twisted pair conductors.

BERT Receiver or "Error Analyzer" Components

For testing using PRBS, the BERT Analyzer relies on its own internal PRBS generator to provide a standard for comparison with the incoming bit stream from the device under test. Transmitters and receivers must be set to the same clock speed and pattern length.

GB1400 User Manual B-7