Intel 820E manual Design Guide 111

Intel® 820E Chipset

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should be kept at least 0.3 inch from the nearest receive trace. Possible exceptions are only where the traces enter or exit the magnetics, the RJ-45/11, and the PLC.

6.Use of an inferior magnetics module. The magnetics modules used by Intel have been fully tested for IEEE PLC conformance, for long-cable BER, and for emissions and immunity. (Inferior magnetics modules often have less common-mode rejection and/or no autotransformer in the transmit channel.)

7.Using an Intel® 82555 or Intel® 82558 component’s physical layer schematic in a PLC design. The transmit terminations and decoupling are different and there also are differences in the receive circuit. Please use the appropriate reference schematic or Application Notes.

8.Failure to use (or incorrect use of) the termination circuits for the unused pins at the RJ-45/11 and for the wire-side center-taps of the magnetics modules. Unused RJ pins and wire-sidecenter-taps must be correctly referenced to chassis ground via the proper-value resistor and a capacitance or termplane. If these are not terminated properly, there can be emissions (i.e., FCC) problems, IEEE conformance issues, and long-cable noise (BER) problems. The Application Notes have schematics that illustrate the proper termination for unused RJ pins and the magnetics center- taps.

9.Incorrect differential trace impedances. It is important to have an approximately 100 Ω impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. It is very common to see customer designs with differential

trace impedances between 75 Ω and 85 Ω , even when the designers think they have designed for 100 Ω . (To calculate differential impedance, many impedance calculators only multiply the single- ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces. When the two traces within a differential pair are kept close to each other (see Note), the edge coupling can lower the effective differential impedance by 5 Ω to 20 Ω . A 10 Ω to 15 Ω drop in impedance is common.) Short traces will have fewer problems if the differential impedance is a little off.

10.Use of an excessively large capacitor between the transmit traces and/or excessive capacitance from the magnetics’ transmit center-tap (on the Intel 82562ET component’s side of the magnetics) to ground. The use of capacitors with capacitances of more than a few pF in either of these locations can slow the 100 Mbps rise and fall time to such a degree that they fail the IEEE rise time and fall time specs, will cause the return loss to fail at higher frequencies, and will degrade the transmit BER performance. Caution is required if a cap is put in either of these locations. If a cap is used, it almost certainly should have a capacitance below 22 pF. (6 pF to 12 pF values have been used in past designs with reasonably good success.) Unless there is some overshoot in the 100 Mbps mode, these caps are unnecessary.

Note: It is important to keep the two traces within a differential pair close to each other, which increases their immunity to crosstalk and other sources of common-mode noise. Keeping them close means lower emissions (i.e., FCC compliance) from the transmit traces as well as an improved receive BER for the receive traces. Close should be considered to be less than 0.030 inches between the two traces within a differential pair. 0.007 inches trace-to-trace spacing is recommended.

Design Guide 111