Intel 820E 2.7.4.2. Suspend-to-RAM Shunt Transistor

Intel® 820E Chipset
R
56 Design Guide
2.7.4.2. Suspend-to-RAM Shunt Transistor
When an Intel 820E chipset system enters or exits Suspend to RAM, power will be ramping to the MCH
(i.e., it will be powering up or powering down). While power is ramping, the states of the MCH outputs
are not guaranteed. Therefore, the MCH could drive the CMOS signals and issue CMOS commands. One
of the commandsthe only one the RDRAMs will respond tois the power-down exit command. To
avoid the MCH inadvertently taking the RDRAMs out of power-down because the CMOS interface is
driven during power ramp, the SCK (CMOS clock) signal must be shunted to gro und when the MCH is
entering and exiting Suspend to RAM. This shunting can be accomplished using the NPN transistor
shown in the circuit in Figure 35. The transistor should have a COBO of 4 pF or less
(i.e., MMBT3904LT1).
In addition, to match the electrical characteristics on the SCK signal, the CMD signal needs a dummy
transistor. This transistor’s base should be tied to ground (i.e., always turned off).
To minimize impedance discontinuities, the traces for CMD and SCK must have a neckdown from
18 mil traces to 5 mil traces, for 175 mils on either side of the SCK/CMD attach point, as shown in
Figure 35.
Figure 35. RDRAM CMOS Shunt Transistor
175 mils
PWROK
SCK
MCH
2N3904
18 mils
wide
175 mils
MCH
18 mils
wide
18 mils
wide
5 mils
wide
175
mils
175
mils
CMD
2N3904
2N3904
VCC5SBY
rdram_cmos_shunt_tran.v
5 mils
wide
18 mils
wide
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