Intel® 820E Chipset

R

Figures

Figure 1. Intel® 820E Chipset Platform Performance Desktop Block Diagram

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Figure 2. Intel® 820E Chipset Platform Performance Desktop Block Diagram

 

(with ISA Bridge)

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Figure 3. Intel® 820E Chipset Platform Dual-Processor Performance Desktop Block

 

Diagram

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Figure 4. (A-C) AC’97 Connections

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Figure 5. MCH 324-Ball µBGA* CSP Quadrant Layout (Top View)

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Figure 6. ICH2 360-Ball EBGA Quadrant Layout (Top View)

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Figure 7. Sample ATX and NLX MCH/ICH2 Component Placement

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Figure 8. Primary-Side MCH Core Routing Example (ATX)

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Figure 9. Secondary-Side MCH Core Routing Example (ATX)

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Figure 10. Data Strobing Example

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Figure 11. Effect of Crosstalk on Strobe Signal

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Figure 12. RIMM Diagram

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Figure 13. RSL Routing Dimensions

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Figure 14. RSL Routing Diagram

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Figure 15. Primary-Side RSL Breakout Example

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Figure 16. Secondary-Side RSL Breakout Example

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Figure 17. Direct RDRAM Termination

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Figure 18. Direct RDRAM* Termination Example

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Figure 19. Incorrect Direct RDRAM* Ground Plane Referencing

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Figure 20. Direct RDRAM* Ground Plane Reference

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Figure 21. Connector Compensation Example

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Figure 22. Section A (See Note), Top Layer

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Figure 23. Section A (See Note), Bottom Layer

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Figure 24. Section B (See Note), Top Layer

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Figure 25. Section B (See Note), Bottom Layer

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Figure 26. Top-Layer CTAB with RSL Signal Routed on the Same Layer (CEFF = 0.8 pF)

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Figure 27. Bottom-Layer CTAB with RSL Signal Routed on the Same Layer

 

(CEFF = 1.35 pF)

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Figure 28. Bottom-Layer CTABs Split across the Top and Bottom Layer to Achieve an

 

Effect CEFF ~1.35 pF

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Figure 29. RSL Signal Layer Alternation

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Figure 30. Example of RDRAM Trace Length Matching

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Figure 31. “Dummy” Via vs. “Real” Via

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Figure 32. RAMREF Generation Example Circuit

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Figure 33. High-Speed CMOS Termination

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Figure 34. SIO Routing Example

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Figure 35. RDRAM CMOS Shunt Transistor

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Figure 36. AGP 2×/4× Routing Example for Interfaces < 6 Inches

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Figure 37. Top Signal Layer

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Figure 38. AGP VDDQ Generation Example Circuit

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Figure 39. AGP 2.0 VREF Generation and Distribution

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Figure 40. AGP Left-Handed Retention Mechanism

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Figure 41. AGP Left-Handed RM Keep-Out Information

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Figure 42. Hub Interface Signal Routing Example

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Figure 43. 8-Bit Hub Interface with a Shared Reference Divider Circuit

 

(Normal/Single Mode)

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Figure 44. 8-Bit Hub Interface with Locally Generated Reference Divider Circuits

 

(Normal/Local Mode)

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Figure 45. Ground Plane Reference (4-Layer Motherboard)

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Figure 46. Combination Host-Side/Device-Side IDE Cable Detection

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Design Guide

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Intel 820E manual Figures