Intel® 820E Chipset

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1.4.Platform Initiatives

1.4.1.Direct Rambus RAM (RDRAM*)

The Direct Rambus RAM (RDRAM) initiative provides the memory bandwidth necessary to obtain optimal performance from the Pentium III processor as well as a high-performance AGP graphics controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz operation. The latter delivers 1.6 GB/s of theoretical memory bandwidth, which is twice the memory bandwidth of 100 MHz SDRAM systems. Coupled with the greater bandwidth, the heavily pipelined RDRAM protocol provides substantially more efficient data transfer. The RDRAM memory interface can utilize more than 95% of the 1.6-GB/s theoretical maximum bandwidth.

In addition to the RDRAM’s performance features, the new memory architecture provides enhanced power management capabilities. The powerdown mode of operation allows Intel 820E chipset-based systems to provide cost-effective support of Suspend to RAM.

1.4.2.Streaming SIMD Extensions

The Pentium III processor provides 70 new streaming SIMD (single-instruction, multiple-data) extensions. The Pentium III processor’s new extensions are floating-point SIMD extensions. Intel® MMX™ technology provides integer SIMD extensions. The Pentium III processor’s new extensions complement the Intel MMX technology SIMD extensions and provide a performance boost to floating- point-intensive 3D applications.

1.4.3.AGP 2.0

In combination with Direct RDRAM memory technology, the AGP 2.0 interface allows graphics controllers to access main memory at over 1 GB/s, which is twice the AGP bandwidth of previous AGP platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with Direct RDRAM and the Pentium III processor’s new streaming SIMD extensions, AGP 2.0 delivers the next level of 3D graphics performance.

1.4.4.Hub Interface

As the I/O speed has increased, the demand placed on the PCI bus by the I/O bridge has become significant. With the addition of AC’97 and ATA/100, coupled with the existing USB, I/O requirements will begin to affect PCI bus performance. The Intel 820E chipset’s hub interface architecture ensures that the I/O subsystem both PCI and the integrated I/O features (IDE, AC’97, USB, etc.) will receive adequate bandwidth. By placing the I/O bridge on the hub interface instead of the PCI, the hub architecture ensures that both the I/O functions integrated into the ICH2 and the PCI peripherals will obtain the bandwidth necessary for peak performance. In addition, the hub interface’s lower pin count allows a smaller package for the MCH and ICH2.

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Design Guide

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Intel 820E manual Platform Initiatives, Direct Rambus RAM Rdram, Streaming Simd Extensions, Agp, Hub Interface