Communication And Network Riser CNR | Intel 820E instruction

8

7

6

5

4

Communication And Network Riser (CNR)

3

2

1

D

VCC3_3SBY

VCC3_3

VCC5SBY

VCC5

A18

B19

J2

+3.3VDUAL

+3.3VD

A16

+12VD

B18

-12V

VCC12

VCC12-

D

C

B

VCC3_3

	10K	R60	10K	R59	10K	R58
	5%		5%		5%

			B15
			A19
	LAN_CLK_CNR		A10
	16		B9
	LAN_RST_CNR
	16		A7
	LAN_TXD2_CNR
	16		B8
	LAN_TXD1_CNR
	16		A8
	LAN_TXD0_CNR
	16		B11
	LAN_RXD2_CNR
	16		A11
	LAN_RXD1_CNR
	16		B12
	LAN_RXD0_CNR
	16
	9,21	EE_SHCLK_ICH2 B22
		EE_DOUT_ICH2	A21
	9,21
		EE_DIN_ICH2	B21
	9,21
		EE_CS_ICH2	A22
	9,15
		SMBCLK_CORE	B25
	4,9,11,38

4,9,11,38	SMBDATA_COREA25
	B24
	A23
	A24
	A3
	A6
	A9
	A14
	A17
	A20
	A30
	B4

+5VDUAL

+5VD

LAN_CLK

LAN_RSTSYNC LAN_TXD2 LAN_TXD1 LAN_TXD0 LAN_RXD2 LAN_RXD1 LAN_RXD0

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

SMB_SCL

SMB_SDA

SMB_A0

SMB_A1

SMB_A2

GND_0

GND_1

GND_2

GND_3

GND_4

GND_5

GND_6

GND_7

LAN

CNR

EEPROM

			AC97_BITCLK	B30
			AC97_BITCLK	B28
			AC97_SYNC	B28
			AC97_SYNC	B29
	AC97_SDATA_OUT			B29
	AC97_SDATA_OUT			A29
	’97AC97_SDATA_IN0			A29
	’97AC97_SDATA_IN0			A28
	ACAC97_SDATA_IN1			A28
	ACAC97_SDATA_IN1			A26
			AC97_RESET#	A26
			AC97_RESET#	B26
			PRIMARY_DN#	B26
			PRIMARY_DN#	A13
			USB+	A13
	USB		USB-	A15
			USB-	B16
			USB_OC#	B16
			USB_OC#
			RESERVE_0	A1
			RESERVE_0	A2
			RESERVE_1	A2
			RESERVE_1	B1
			RESERVE_2	B1
			RESERVE_2	B2
			RESERVE_3	B2
			RESERVE_3	A4
			RESERVE_4	A4
			RESERVE_4	A5
			RESERVE_5	A5
			RESERVE_5	B5
			RESERVE_6	B5
			RESERVE_6	B6
			RESERVE_7	B6
			RESERVE_7	A12
			RESERVE_8	A12
			RESERVE_8	A27
			RESERVE_9	A27
			RESERVE_9	B14
			RESERVE_10	B14
			RESERVE_10	B3
			RESERVE_11	B3
			RESERVE_11
			GND_8	B7
			GND_8	B10
			GND_9	B10
			GND_9	B13
			GND_10	B13
			GND_10	B17
			GND_11	B17
			GND_11	B20
			GND_12	B20
			GND_12	B23
			GND_13	B23
			GND_13	B27
			GND_14	B27
			GND_14

		R61		0K		AC_BITCLK
						AC_BITCLK
AC_SYNC_CNR			16
AC_SDATAOUT_CNR			16
AC_SDATAOUT_CNR			16
			16	R62
				R62
		R63		33		5%
		33	5%
			XREF=8			PRIMARY_DN#
						USB+_CNR
						28
						USB-_CNR
						28
						USB_OC#_CNR
		5%				28
C285		5%		C78		5%
C285
5%	R73	15K			R64	15K
5%	R73	15K		47PF	R64	15K
47PF
50V				5%
				50V

		9,13
R57	10K	No Stuff
		R78	10K

AC_SDATAIN0_CNR 16

AC_SDATAIN1_CNR

9

AC_RESET#_ICH2

C

B

A

J18

1 2

3 4

56

7 8

EE_CS_ICH2 9,15

EE_CS_ICH2_OB

21

	10K	R75
	5%	R75
	5%

	VCC3_3
U21		U21		U21
U21		SN74HC03		SN74HC03
SN74HC03		9	14VCC	4	14VCC	AC_REST#_ICH2
1	14VCC	10	8	5	6	AC_REST#_ICH2
2	3	10		5
2			7 GND		7 GND
	7 GND		7 GND		7 GND
	7 GND
R85
10K

A

8

7

6

5

4

	TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD							REV:
	COMMUNICATION AND NETWORK RISER (CNR)					DRAWN BY:	0.5
			R	PCG PLATFORM DESIGN		DRAWN BY:		PROJECT:
			R	PCG PLATFORM DESIGN		PCG AE		Camino2
				1900 PRAIRIE CITY ROAD		PCG AE		Camino2
				FOLSOM, CALIFORNIA 95630		LAST REVISED:		SHEET:
				FOLSOM, CALIFORNIA 95630	3-20-2000_14:56			15 OF 40
3				2	3-20-2000_14:56		1	15 OF 40
3				2			1

Image 211

Intel 820E manual Communication And Network Riser CNR

Contents

Design Guide Intel 820E Chipset Intel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Mil Stack-Up Tables 135 Rev Description Date Revision History About This Design Guide Introduction Reference Documents System Overview Memory Controller Hub MCH Chipset ComponentsController Hub 2 ICH2 Intel 820E Chipset Platform Bandwidth Summary FWH Flash BiosBandwidth Summary ISA Bridge MCH System Configuration UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs AGP Platform InitiativesDirect Rambus RAM Rdram Streaming Simd Extensions Manageability Integrated LAN ControllerUltra ATA/100 Support Expanded USB Support Interrupt Controller Function DisableIntruder Detect SMBus 9. AC’97 Ebga C AC’97 Connections Low-Pin-Count LPC Interface This page is intentionally left blank Component Quadrant Layout General Recommendations MCH Sample ATX and NLX MCH/ICH2 Component Placement Intel 820E Chipset Component Placement Primary-Side MCH Core Routing Example ATX Core Chipset Routing Recommendations Secondary-Side MCH Core Routing Example ATX Data Strobing Example Source-Synchronous Strobing Data Associated Strobe Differential Clocking/StrobingDirect RDRAM* Interface AGP 2× Data/Strobe Association Direct RDRAM* Layout Guidelines Stack-Up RSL Routing Placement Guidelines for Motherboard Routing LengthsReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example Direct Rdram Termination RSL Termination Direct RDRAM* Termination Example Direct RDRAM* Ground Plane Reference GND Plane Plane Equation 1. Approximate Copper Tab Area Calculation Direct RDRAM* Connector Compensation Copper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer Section B See Note, Bottom Layer RSL and Clocking Signal Routing Layer Capacitance pF Flood Signal RSL Signal Layer Alternation RSL Routing Layer Requirements Length Matching Methods Equation 3. Rdram Clock Signal Trace Length Calculation Equation 2. Rdram RSL Signal Trace Length Calculation Length Matching and Via Compensation Example Via Compensation Signal Ball on Nominal Package High-Speed Cmos Routing Direct RDRAM* Reference Voltage High-Speed Cmos Termination SIO Routing Rdram Cmos Shunt Transistor Suspend-to-RAM Shunt Transistor Direct RDRAM* Clock Routing Direct RDRAM* Design ChecklistSignal List RSL Signals High-Speed Serial Clocks Intel 820E Chipset Primary side If Signal Routed from MCH AGP AGP Interface Signal Groups Signal Groups AGP 2.0 Data/Strobe Associations 2 × Timing Domain Routing Guidelines3 ×/4× Timing Domain Routing Guidelines Interfaces 6 Inches AGP 2×/4× Routing Example for Interfaces 6 Inches Interfaces 6 Inches and 7.25 Inches AGP 2.0 Routing Summary1,2 Signal Maximum Trace Spacing Length Relative ToAGP 2.0 Routing Summary All AGP Interfaces Decoupling AGP Clock RoutingGeneral AGP Routing Guidelines Recommendations Ground Reference Vddq Generation and TYPEDET# TYPEDET# on Add-in Card DDQ Supplied by MB TYPDET#/VDDQ Relationship AGP Vddq Generation Example Circuit Vref Generation for AGP 2.0 2× and 4× AGP 2.0 Vref Generation and Distribution AGP Pull-Ups Compensation16 k Ω Motherboard / Add-in Card Interoperability AGP Signal Voltage Tolerance ListConnector / Add-in Card Interoperability Connector Universal Connector AGP Left-Handed Retention Mechanism AGP Universal Retention Mechanism RM AMP P/N AGP Left-Handed RM Keep-Out Information Hub Interface Hub Interface Signal Routing Example Bit Hub Interface Routing Guidelines Bit Hub Interface Data SignalsBit Hub Interface Strobe Signals Bit Hub Interface Buffer Configuration Setting MCH ICH2 Hlrefa Hubref Bit Hub Interface Hubref Generation Circuit Specifications Component Hub Interface Trace Rcomp Resistor Value Bit Hub Interface CompensationBit Hub Interface Decoupling Guidelines Bit Hub Interface Rcomp Resistor Values System Bus Ground Plane Reference Additional Host Bus GuidelinesMinimizing Crosstalk on the AGTL+ Interface Additional Considerations IDE InterfaceCable Combination Host-Side/Device-Side Cable Detection Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side IDE Cable Detection Device-Side IDE Cable Detection Device-Side Cable Detection Primary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# Sddreq Secondary IDE Connector RequirementsSiordy IRQ15 SDDACK# ICH2 AC’97- Codec Connection 13. AC’97 Intel 820E Chipset Motherboard CNR Board CNR AC97RESET# Signal DescriptionsCDCDNENAB# Invalid Codec Configurations Valid Codec ConfigurationsCodec Configurations Valid Codec Configurations 13.3. AC’97 Routing USB Using Native USB InterfaceMotherboard Implementation ISA Support Recommended USB trace characteristicsDisabling the Native USB Interface of ICH2 SMBus/SMLink Interface 16. I/O Apic Design Recommendation SMBus / SMLink Use Implementation Pull-Up Requirements for SMBus and SMLink Signals RTC PCI External Capacitors RTC Crystal RTC Layout Considerations RTC External Battery Connection Rtcrst External Circuit for ICH2 RTC RTC External Rtcrst Circuit RTC-Well Input Strap Requirements Spkr Pin ConsiderationRTC Routing Guidelines Vbias DC Voltage and Noise Measurements ICH2 Pirq Routing Function in ICH2 using the PCI IRQ in IoapicUsage of I/O Apic Interrupt Inputs 16 through PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd LAN Connect Component Connection FeaturesLAN Layout Guidelines PIRQA# PIRQB# PIRQC# PIRQD# LAN Design Guide Section Reference ICH2 LAN Interconnect GuidelinesLayout Section Previous Design Guide Section Point-to-Point Interconnect Bus TopologiesLOM/CNR Interconnect Configuration Signal Routing and LayoutLength Requirements for Figure Impedances Crosstalk ConsiderationLine Termination General Trace Routing Considerations General LAN Routing Guidelines and Considerations Trace Geometry and Length Power and Ground Connections Ground Plane Separation Layer Board Design Design Guide 111 Related Documents Guidelines for Intel 82562EH Component PlacementIntel 82562EH Home/PNA* Guidelines Crystals and Oscillators Intel 82562EH Component Termination Phoneline Hpna Termination Distance Priority Guideline Critical DimensionsLPF Eeprom Distance from LPF to Phone RJ11 Intel 82562ET / Intel 82562EM Component Guidelines Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Terminating Unused Connections Reducing Circuit Inductance LAN Disable Circuit Intel 82562ET/EM Disable Guidelines Lancl Dual-Footprint Analog Interface ICH2 Decoupling Recommendations Power Plane/Pins # Decoupling Capacitor ValueDecoupling Capacitor Recommendation Decoupling Capacitor Layout In-Circuit FWH Flash Bios Programming FWH Flash Bios GuidelinesFWH Flash Bios VPP Design Guidelines Checklist Items Recommendations Reason/Effect ICH2 Design ChecklistPCI Interface Eeprom Interface FWH Flash Bios InterfaceHub Interface LAN Interface PIRQ#E Interrupt InterfacePIRQ#DA PIRQ#H USB Interface GpioVCCSUS3.3 Processor Signals RTC System ManagementAC’97 5VREF SUS Miscellaneous SignalsPower Spkr IDE Checklist Checklist Items ISA Bridge ChecklistICH2 AD22 / ISA USB ICH2 Layout ChecklistBit Hub Interface IDE Interface LAN Connect I/F ICH2 Decoupling Layout Recommendations Yes CK-SKS Clocking 138 Design Guide Term Definition Terminology and Definitions 140 Design Guide Guideline Methodology AGTL+ Design Guidelines Equation 6. Maximum Flight Time Equation 4. Setup TimeInitial Timing Analysis Equation 5. Hold Time IC Parameters Pentium Intel AGTL+ Parameters for Example Calculations1,2 Driver Receiver Clk Example Tfltmax Calculations for 133 MHz Bus1 Sensitivity Analysis Determine the Desired General Topology, Layout, and RoutingPre-Layout Simulation Methodology Simulation Criteria Monte Carlo Analysis Place and Route Board Estimate Component-to-Component Spacing for AGTL+ SignalsLayout and Route Board Trace Width Space Guidelines Host Clock Routing Apic Data Bus RoutingCrosstalk Type Trace WidthSpace Ratio Post-Layout Simulation Intersymbol Interference Crosstalk Analysis ValidationMeasurements Flight Time Simulation Flight Time Hardware Validation Equation 8. Valid Delay EquationSET Q CLR Q AGTL+ TheoryTiming Requirements Aggressor and Victim Networks Crosstalk Theory Potential Termination Crosstalk Problems Textbook Timing Equations More Details and Insight Effective Impedance and Tolerance/Variation Power Distribution Reference Planes and PCB Stack-Up One Signal Layer and One Reference Plane Layer Switch with Multiple Reference Planes Same Type One Layer with Multiple Reference Planes High-Frequency Decoupling Clock Routing Ringback Levels Vref Guard BandOverdrive Region Flight Time Definition and Measurement Conclusion Intel 820E Chipset Platform System Clocks Clock GenerationNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Relationship Skew Pin-to-Pin ps Board ps Total ps Min Max Intel 820E Chipset Platform Clock SkewsLPCCLK, Pciclk ±TBD3 Intel 820E Chipset Clock Routing Guidelines1,2 CK133/DRCG Pin Name Component Intel 820E Chipset Platform System Clock Cross-Reference 1 .318 MHz Crystal to CK133 Component Placement and Interconnection Layout Requirements2. CK133 to Drcg MCH to Drcg MCH-to-DRCG Routing Diagram Clock From Length inches Section DRCG-to-RDRAM ChannelTrace Length Trace Geometry Differential Clock Routing Diagram Sections A, C & D CMID, CMID2 Drcg Impedance Matching CircuitExternal Drcg Component Values1,2 Component Nominal Value Drcg Layout Example AGP Clock Routing GuidelinesClock Routing Guidelines for Intel PGA370 Designs Series Termination Resistors for CK133 Clock Outputs Buffer Name CC Range Impedance If Unused Output Unused OutputsDecoupling Recommendation for CK133 and Drcg Unused Output Termination Drcg Frequency Selection and the DRCG+ Drcg Frequency Selection Table and Jitter Specification DRCG+ Frequency Selection DRCG+ Frequency Selection Schematic PCB Materials Stack-Up Requirement Test Coupon Design Guidelines Design Process Sample SM max Resin % Recommended Stack-UpInner-Layer Routing Stack-Up Examples Field Solver vs. Zcalc Impedance Calculation Tools Board Impedance/Stack-up Summary Testing Board Impedance 182 Design Guide Terminology and Definitions Power DeliveryTerm Definition Intel 820E Chipset Power Delivery Example VCC Dual Switch Vbsy 3VSB V and 2.5 V Power Sequencing Schottky Diode VSB ICH2 1.8 V / 3.3 V Power Sequencing 4 .3V/V5REF Sequencing Example 1.8V/3.3V Power Sequencing Circuit Option 1 Reduce the Clock Frequency During Initialization Excessive Power Consumption by 64/72-Mbit RdramVref Use a GPO to Reduce Drcg Frequency Example of ICH2 Power Plane Split ICH2 Power Plane Split Component Thermal Design Power 133/400 MHz Thermal Design PowerFeatures Intel 820E Chipset Component Thermal Design Power Vendor Intel Contact Contact Information Glue Chip Vendors Reference Design Feature Set Appendix a Reference Design Schematics Uniprocessor 196 Design Guide FOLSOM, California Last Revised Sheet REVDrawn by PCG Platform Design Project PCG AE Prairie City Road Device Table Block Diagram AL9 AK8AH8 AN9 Tckr TDI Tmsr CPURST#R2 DBRESET#VCMOS15 Gtlref Clock Synthesizer Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host Hubref RamrefrRamref Connagpref GAD2 GAD3 GAD0GAD0 GAD1 GAD1 GAD2 AD3 AD0AD1 AD2 Rtcrstjp ACRESET#CR4 Vbatcr 1UF VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 NC1 GndaFwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36 NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 Rimm LDQA0 SWP RSRV4/RESETRSRV4/RESET SWP TERMDQA80 Super I/O AC’97 Audio DB15AUDSTK Micinr MicinfbMicin Micinc Communication And Network Riser CNR ACSDATAIN0CNR Acsynccnr Acsdataoutcnr Stubs on AC97 LinkACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2 RP7 LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH H1138ARAGONITE LAN RJ45 For 82562ET/EMLanactled LAN Option Intel PART# 25MHZY5 Xtal Y2 Xtal LANCLKX1 R381LANCLKX2 Stuff for 82562EH VCC12 Irtx Power SWPower LED SW1 Agpclkconn B7 CLK AGP4XU20 AGPOC#TYPEDET# USBAGP+ B4 Usbagp Ptdi VCC5 VCC12PCI3CON PTRST# Ptck Ptms PCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr Game Port Imax VRM G1 VRM G2 VRM Fault VRM IFBFAULT# IFB Vccvid REV Project Voltage Regulators SBY ITH R 1UF-X7RVCC33SBYTG VCC33SBYSW VCC25SBY VCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH Power Connector HREQ#0 BPRI# DBSY# PCI/AGP Pullups/Pulldowns Termcmd Termsck Rambus* Termination Decoupling Bulk Decoupling Drawn by PCG Platform Design Project PCG AE VCMOS18SBY Revision History Drawn by PCG Platform Design Project PCG AE Revision History HL8 HL4 HL5 HL6 HL7 Hub Interface Connector For debug onlyProbe Connector TESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB#