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Intel 820E manual LAN RJ45 For 82562ET/EM, H1138ARAGONITE, Lanactled

Models: 820E

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LAN (RJ45 For 82562ET/EM)

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						LAN_LILED		1	2
						17,18,19		CR11
								CR11
		NOTE: Do not stuff C329
18,19	LAN_TDP							J16
				H1138_ARAGONITE				J16
								RJ45
							1	RJ45		2
			16	U27	TXP 10		1	P1	P2	2
C		C329	16	TDP	TXP 10		3	P1	P2	4			C
		C329	14 TDC		CMT 12		5	P3	P4	6			C
18,19	LAN_TDM	0.1UF	15 TDM		TXM 11		7	P5	P6	8
			13 NC13		NC9 9		9	P7	P8	10
			4	NC4	NC8 8		11	P9	P10	12	VCC3_3SBY
18,19,21	LAN_RDP		1	RDP/CHIP+	RXP/RING	7	13	P11	P12	14
18,19,21	LAN_RDM		2	RDM//CHIP-	RXM/TIP	6	15	P13	P14	16
			3	RDC/GND	RXC 5			P15	P16
		C318							R113		LAN_SPEEDLED
									R113		LAN_SPEEDLED
		0.1UF										17,18,19
									330
											R334	LAN_ACTLED	B
B							RP54					18,19	B
B						1	RP54				330
						1	8				330
						2	7
						3	6
						4	5
						75
								R125
								10M
								5%

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TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD					REV:
LAN (RJ45)				DRAWN BY:	0.5
		R	PCG PLATFORM DESIGN	DRAWN BY:	PROJECT:
		R	PCG PLATFORM DESIGN	PCG AE	Camino2
			1900 PRAIRIE CITY ROAD	PCG AE	Camino2
			FOLSOM, CALIFORNIA 95630	LAST REVISED:	SHEET:
			FOLSOM, CALIFORNIA 95630	3-20-2000_16:55	20 OF 40
				3-20-2000_16:55	20 OF 40

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Intel 820E manual LAN RJ45 For 82562ET/EM, H1138ARAGONITE, Lanactled

Contents

Intel 820E Chipset Design GuideIntel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Tables Mil Stack-Up135 Revision History Rev Description DateIntroduction About This Design GuideReference Documents System Overview Chipset Components Memory Controller Hub MCHController Hub 2 ICH2 FWH Flash Bios Bandwidth SummaryISA Bridge Intel 820E Chipset Platform Bandwidth SummarySystem Configuration MCHUltraATA/100/66/33 USB Ports 2 HC AC97 Codecs Platform Initiatives Direct Rambus RAM RdramStreaming Simd Extensions AGPIntegrated LAN Controller Ultra ATA/100 SupportExpanded USB Support ManageabilityFunction Disable Intruder DetectSMBus Interrupt Controller9. AC’97 C AC’97 Connections EbgaLow-Pin-Count LPC Interface This page is intentionally left blank General Recommendations Component Quadrant LayoutMCH Intel 820E Chipset Component Placement Sample ATX and NLX MCH/ICH2 Component PlacementCore Chipset Routing Recommendations Primary-Side MCH Core Routing Example ATXSecondary-Side MCH Core Routing Example ATX Source-Synchronous Strobing Data Strobing ExampleDifferential Clocking/Strobing Direct RDRAM* InterfaceAGP 2× Data/Strobe Association Data Associated StrobeStack-Up Direct RDRAM* Layout GuidelinesPlacement Guidelines for Motherboard Routing Lengths RSL RoutingReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example RSL Termination Direct Rdram TerminationDirect RDRAM* Ground Plane Reference Direct RDRAM* Termination ExamplePlane GND PlaneDirect RDRAM* Connector Compensation Equation 1. Approximate Copper Tab Area CalculationCopper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer RSL and Clocking Signal Routing Layer Capacitance pF Section B See Note, Bottom LayerFlood Signal RSL Signal Layer Alternation Length Matching Methods RSL Routing Layer RequirementsEquation 2. Rdram RSL Signal Trace Length Calculation Equation 3. Rdram Clock Signal Trace Length CalculationVia Compensation Length Matching and Via Compensation ExampleSignal Ball on Nominal Package Direct RDRAM* Reference Voltage High-Speed Cmos RoutingSIO Routing High-Speed Cmos TerminationSuspend-to-RAM Shunt Transistor Rdram Cmos Shunt TransistorDirect RDRAM* Design Checklist Signal ListRSL Signals High-Speed Serial Clocks Direct RDRAM* Clock RoutingIntel 820E Chipset If Signal Routed from MCH Primary sideAGP Interface Signal Groups AGPSignal Groups 2 × Timing Domain Routing Guidelines 3 ×/4× Timing Domain Routing GuidelinesInterfaces 6 Inches AGP 2.0 Data/Strobe AssociationsInterfaces 6 Inches and 7.25 Inches AGP 2×/4× Routing Example for Interfaces 6 InchesSignal Maximum Trace Spacing Length Relative To AGP 2.0 Routing SummaryAll AGP Interfaces AGP 2.0 Routing Summary1,2AGP Clock Routing General AGP Routing GuidelinesRecommendations DecouplingVddq Generation and TYPEDET# Ground ReferenceTYPDET#/VDDQ Relationship TYPEDET# on Add-in Card DDQ Supplied by MBVref Generation for AGP 2.0 2× and 4× AGP Vddq Generation Example CircuitAGP 2.0 Vref Generation and Distribution Compensation AGP Pull-Ups16 k Ω AGP Signal Voltage Tolerance List Connector / Add-in Card InteroperabilityConnector Universal Connector Motherboard / Add-in Card InteroperabilityAGP Universal Retention Mechanism RM AGP Left-Handed Retention MechanismAGP Left-Handed RM Keep-Out Information AMP P/NHub Interface Signal Routing Example Hub InterfaceBit Hub Interface Data Signals Bit Hub Interface Strobe SignalsBit Hub Interface Buffer Configuration Setting Bit Hub Interface Routing GuidelinesBit Hub Interface Hubref Generation Circuit Specifications MCH ICH2 Hlrefa HubrefBit Hub Interface Compensation Bit Hub Interface Decoupling GuidelinesBit Hub Interface Rcomp Resistor Values Component Hub Interface Trace Rcomp Resistor ValueAdditional Host Bus Guidelines System Bus Ground Plane ReferenceMinimizing Crosstalk on the AGTL+ Interface IDE Interface Additional ConsiderationsCable Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side Cable DetectionCombination Host-Side/Device-Side IDE Cable Detection Device-Side Cable Detection Device-Side IDE Cable DetectionPrimary IDE Connector Requirements Secondary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# SddreqSiordy IRQ15 SDDACK# 13. AC’97 ICH2 AC’97- Codec ConnectionIntel 820E Chipset Motherboard CNR Board CNR Signal Descriptions AC97RESET#CDCDNENAB# Valid Codec Configurations Codec ConfigurationsValid Codec Configurations Invalid Codec Configurations13.3. AC’97 Routing Using Native USB Interface USBMotherboard Implementation Recommended USB trace characteristics ISA SupportDisabling the Native USB Interface of ICH2 16. I/O Apic Design Recommendation SMBus/SMLink InterfacePull-Up Requirements for SMBus and SMLink Signals SMBus / SMLink Use ImplementationPCI RTCRTC Crystal External CapacitorsRTC External Battery Connection RTC Layout ConsiderationsRTC External Rtcrst Circuit Rtcrst External Circuit for ICH2 RTCSpkr Pin Consideration RTC Routing GuidelinesVbias DC Voltage and Noise Measurements RTC-Well Input Strap RequirementsFunction in ICH2 using the PCI IRQ in Ioapic ICH2 Pirq RoutingUsage of I/O Apic Interrupt Inputs 16 through LAN Connect Component Connection Features LAN Layout GuidelinesPIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc IntdICH2 LAN Interconnect Guidelines LAN Design Guide Section ReferenceLayout Section Previous Design Guide Section Bus Topologies Point-to-Point InterconnectLOM/CNR Interconnect Signal Routing and Layout ConfigurationLength Requirements for Figure Crosstalk Consideration ImpedancesLine Termination General LAN Routing Guidelines and Considerations General Trace Routing ConsiderationsPower and Ground Connections Trace Geometry and LengthGround Plane Separation Layer Board Design Design Guide 111 Guidelines for Intel 82562EH Component Placement Intel 82562EH Home/PNA* GuidelinesCrystals and Oscillators Related DocumentsPhoneline Hpna Termination Intel 82562EH Component TerminationCritical Dimensions LPFEeprom Distance Priority GuidelineIntel 82562ET / Intel 82562EM Component Guidelines Distance from LPF to Phone RJ11Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Reducing Circuit Inductance Terminating Unused ConnectionsIntel 82562ET/EM Disable Guidelines LAN Disable CircuitLancl Dual-Footprint Analog Interface Power Plane/Pins # Decoupling Capacitor Value ICH2 Decoupling RecommendationsDecoupling Capacitor Recommendation Decoupling Capacitor Layout FWH Flash Bios Guidelines In-Circuit FWH Flash Bios ProgrammingFWH Flash Bios VPP Design Guidelines ICH2 Design Checklist Checklist Items Recommendations Reason/EffectPCI Interface FWH Flash Bios Interface Hub InterfaceLAN Interface Eeprom InterfaceInterrupt Interface PIRQ#DAPIRQ#H PIRQ#EGpio USB InterfaceVCCSUS3.3 Processor Signals System Management RTCAC’97 Miscellaneous Signals PowerSpkr 5VREF SUSIDE Checklist ISA Bridge Checklist Checklist ItemsICH2 AD22 / ISA ICH2 Layout Checklist Bit Hub InterfaceIDE Interface USBLAN Connect I/F ICH2 Decoupling CK-SKS Clocking Layout Recommendations Yes138 Design Guide Terminology and Definitions Term Definition140 Design Guide AGTL+ Design Guidelines Guideline MethodologyEquation 4. Setup Time Initial Timing AnalysisEquation 5. Hold Time Equation 6. Maximum Flight TimeAGTL+ Parameters for Example Calculations1,2 IC Parameters Pentium IntelExample Tfltmax Calculations for 133 MHz Bus1 Driver Receiver ClkDetermine the Desired General Topology, Layout, and Routing Pre-Layout SimulationMethodology Sensitivity AnalysisMonte Carlo Analysis Simulation CriteriaEstimate Component-to-Component Spacing for AGTL+ Signals Place and Route BoardLayout and Route Board Host Clock Routing Apic Data Bus Routing Trace Width Space GuidelinesCrosstalk Type Trace WidthSpace Ratio Intersymbol Interference Post-Layout SimulationValidation Crosstalk AnalysisMeasurements Flight Time Simulation Equation 8. Valid Delay Equation Flight Time Hardware ValidationSET Q CLR Q Theory AGTL+Timing Requirements Crosstalk Theory Aggressor and Victim NetworksPotential Termination Crosstalk Problems More Details and Insight Textbook Timing EquationsPower Distribution Effective Impedance and Tolerance/VariationOne Signal Layer and One Reference Plane Reference Planes and PCB Stack-UpLayer Switch with Multiple Reference Planes Same Type High-Frequency Decoupling One Layer with Multiple Reference PlanesClock Routing Vref Guard Band Ringback LevelsOverdrive Region Conclusion Flight Time Definition and MeasurementClock Generation Intel 820E Chipset Platform System ClocksNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Intel 820E Chipset Platform Clock Skews Relationship Skew Pin-to-Pin ps Board ps Total ps Min MaxLPCCLK, Pciclk Intel 820E Chipset Clock Routing Guidelines1,2 ±TBD3Intel 820E Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name ComponentComponent Placement and Interconnection Layout Requirements 1 .318 MHz Crystal to CK1332. CK133 to Drcg MCH-to-DRCG Routing Diagram MCH to DrcgDRCG-to-RDRAM Channel Trace LengthTrace Geometry Clock From Length inches SectionDifferential Clock Routing Diagram Sections A, C & D Drcg Impedance Matching Circuit External Drcg Component Values1,2Component Nominal Value CMID, CMID2AGP Clock Routing Guidelines Clock Routing Guidelines for Intel PGA370 DesignsSeries Termination Resistors for CK133 Clock Outputs Drcg Layout ExampleUnused Outputs Decoupling Recommendation for CK133 and DrcgUnused Output Termination Buffer Name CC Range Impedance If Unused OutputDrcg Frequency Selection Table and Jitter Specification Drcg Frequency Selection and the DRCG+DRCG+ Frequency Selection Schematic DRCG+ Frequency SelectionStack-Up Requirement PCB MaterialsDesign Process Test Coupon Design GuidelinesRecommended Stack-Up Inner-Layer RoutingStack-Up Examples Sample SM max Resin %Impedance Calculation Tools Field Solver vs. ZcalcTesting Board Impedance Board Impedance/Stack-up Summary182 Design Guide Power Delivery Terminology and DefinitionsTerm Definition Intel 820E Chipset Power Delivery Example Dual Switch VCCVbsy V and 2.5 V Power Sequencing Schottky Diode 3VSBICH2 1.8 V / 3.3 V Power Sequencing VSBExample 1.8V/3.3V Power Sequencing Circuit 4 .3V/V5REF SequencingExcessive Power Consumption by 64/72-Mbit Rdram Option 1 Reduce the Clock Frequency During InitializationVref Use a GPO to Reduce Drcg Frequency ICH2 Power Plane Split Example of ICH2 Power Plane SplitThermal Design Power FeaturesIntel 820E Chipset Component Thermal Design Power Component Thermal Design Power 133/400 MHzGlue Chip Vendors Vendor Intel Contact Contact InformationAppendix a Reference Design Schematics Uniprocessor Reference Design Feature Set196 Design Guide REV Drawn by PCG Platform Design Project PCG AEPrairie City Road FOLSOM, California Last Revised SheetBlock Diagram Device TableAK8 AH8AN9 AL9CPURST#R2 DBRESET# VCMOS15Gtlref Tckr TDI TmsrClock Synthesizer Hubref Ramrefr RamrefConnagpref Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa HostGAD0 GAD0 GAD1GAD1 GAD2 GAD2 GAD3AD0 AD1AD2 AD3ACRESET# CR4Vbatcr 1UF RtcrstjpNC1 Gnda Fwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29SWP RSRV4/RESET RSRV4/RESET SWPTERMDQA80 Rimm LDQA0Super I/O AC’97 Audio Micinr Micinfb MicinMicinc DB15AUDSTKCommunication And Network Riser CNR Stubs on AC97 Link ACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2RP7 ACSDATAIN0CNR Acsynccnr AcsdataoutcnrLAN 82562EH 82562ET/EM LAN RJ11 For 82562EH LAN RJ45 For 82562ET/EM H1138ARAGONITELanactled 25MHZ Y5 Xtal Y2 Xtal LANCLKX1R381LANCLKX2 LAN Option Intel PART#Stuff for 82562EH Power SW Power LEDSW1 VCC12 IrtxAGP4XU20 AGPOC# TYPEDET#USBAGP+ B4 Usbagp Agpclkconn B7 CLKVCC5 VCC12 PCI3CON PTRST# PtckPtms PtdiPCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy Game Port VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR MidiinrVRM Fault VRM IFB FAULT# IFBVccvid REV Project Imax VRM G1 VRM G2Voltage Regulators 1UF-X7R VCC33SBYTG VCC33SBYSW VCC25SBYVCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH SBY ITH RPower Connector BPRI# DBSY# HREQ#0PCI/AGP Pullups/Pulldowns Rambus* Termination Termcmd TermsckDecoupling VCMOS18SBY Bulk Decoupling Drawn by PCG Platform Design Project PCG AERevision History Revision History Drawn by PCG Platform Design Project PCG AEHub Interface Connector For debug only Probe ConnectorTESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB# HL8 HL4 HL5 HL6 HL7