Intel® 820E Chipset

R

Figure 38. AGP VDDQ Generation Example Circuit

 

 

 

 

 

 

 

+3.3V

 

VDDQ

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

 

+12V

 

 

 

 

 

 

C2

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

47 µF

 

 

 

 

U1

LT1575

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

SHDN

 

IPOS

5

 

5

 

 

 

2

 

6

 

 

 

 

 

 

 

 

C3

 

 

VIN

 

INEG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R2

220 µF

R1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

GND

 

GATE

7

 

 

 

1 k

 

 

 

 

 

 

4

 

 

 

8

 

 

 

 

C1

FB

 

COMP

 

 

 

 

 

 

 

 

 

 

 

1 µF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C4

 

 

 

 

 

 

 

 

 

10 pF

 

 

 

 

 

 

 

C5

 

R5

 

 

 

 

 

 

 

47 µF

7.5 k

 

 

 

 

 

 

 

 

 

 

 

 

R3

 

 

 

 

 

 

 

 

 

301

TYPEDET#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R4

 

 

 

 

 

 

 

 

 

1.21 k

 

 

 

 

 

 

 

 

 

agp_vddq_generation.vsd

2.8.8.VREF Generation for AGP 2.0 (2× and 4×)

VREF generation for AGP 2.0 will differ, depending on the AGP card type used. The 3.3 V AGP cards generate VREF locally (i.e., they have a resistor divider on the card that divides VDDQ down to VREF), as shown in Figure 39. To account for potential differences between VDDQ and GND at the MCH and graphics controller, 1.5 V cards use a source-generated VREF. (i.e., the VREF signal is generated at the graphics controller and sent to the MCH, and another VREF is generated at the MCH and sent to the graphics controller.).

Both the graphics controller and the MCH are required to generate VREF and distribute it through the connector (1.5 V add-in cards only). Two pins are defined on the AGP 2.0 universal connector to allow this VREF passing, as follows:

VREFGC:

VREF from the graphics controller to the chipset

VREFCG:

VREF from the chipset to the graphics controller

To preserve the common-mode relationship between the VREF and data signals, the routing of the two

VREF signals must be matched in length to the strobe lines, within 0.5 inch on the motherboard and within 0.25 inch on the add-in card.

The voltage-divider networks consist of AC and DC elements, as shown in Figure 39.

The VREF divider network should be placed as close as practical to the AGP interface, to obtain the benefit of the common-mode power supply. However, the trace spacing around the VREF signals must be a minimum of 25 mils, to reduce crosstalk and maintain signal integrity.

68

Design Guide

Page 68
Image 68
Intel 820E manual Vref Generation for AGP 2.0 2× and 4×, AGP Vddq Generation Example Circuit