Intel 820E manual Decoupling

8 7

6 5 4 3 2 1

D

C

Decoupling

MCH Decoupling

VCC1_8

C157	0.1UF
C212	0.1UF
C201	0.1UF
C156	0.01UF
C213	0.01UF
C202	0.01UF
C221	0.1UF
C197	0.1UF

MCH Decoupling VCC1_8

C361	0.1UF
C359	0.1UF
C360	0.1UF
C362	0.1UF

Backside No Stuff

NOTE: Place VDDQ decoupling as close to the MCH as possible

FCPGA VCC_CORE Decoupling

ICH Decoupling

82559 Decoupling

FCPGA Vtt Decoupling

VDDQ

VCC3_3

VCC3_3SBY

VTT1_5

VTT1_5

C166 C162 C368 C367 C343 C344

0.01UF

C252 C230 C224 C254 C248 C232 C231 C253

0.1UF

C290 C88 C105 C60 C29 C30

VCCVID

VCCVID

0.1UF

C454 C453 C452 C451 C448 C449 C450

0.1UF

C464 C463 C462 C461 C460 C459 C458

0.1UF

0.01UF

0.1UF

0.1UF

C134 C139 C131 C136 C137

4.7UF

C133 C138 C132 C141 C135

4.7UF

D

0.1UF

0.1UF

0.1UF

0.01UF

0.1UF

4.7UF

4.7UF

0.1UF

0.1UF

0.1UF

0.01UF

0.1UF

4.7UF

4.7UF

0.1UF

0.1UF

0.01UF

4.7UF

4.7UF

4.7UF

0.1UF

0.1UF

0.01UF

0.01UF

4.7UF

4.7UF

4.7UF

0.1UF

0.1UF

0.01UF

0.01UF

0.01UF

0.1UF

0.1UF

C414

0.01UF

All 4.7uF capacitors should be 1206 package size placed

C455

0.1UF

C465

0.1UF

within the PGA370 socket cavity on componet side of PCB.

C415

0.01UF

C456

0.1UF

C466

0.1UF

C

C457

0.1UF

Backside No Stuff - C414,C415

B

A

For chipset decoupling, use 0.1UF and 0.01UF decoupling capacitor

at each corner of the device. If there is room, also add 0.01UF capacitor in the middle of each quad. Place additional caps if routable.

VCC3_3SBY
U15 14		10
11
74LVC14A7			VCC5SBY
			U18
			74LS132	14VCC
			1
			2	3
				7 GND
VCC3_3SBY
9	14	U3	U18
		8
10			74LS132	14VCC
			12
SN74LVC08A			13	11

7 GND

8 7

									VCC3_3SBY		VCC3_3SBY
		VCC3_3SBY			VCC3_3			U23			SN74LVC02A
Un-used Gates										U24
								SN74HC03
								4	14 VCC		4
								5
									6	5	14VCC
					U19				7 GND	6	B
						VCC					7 GND
					3	14	4
		U14	VCC		7	GND
					SN74LVC07A			U23			SN74LVC02A
VCC3_3SBY		9	14	8						U24
								SN74HC03
								9	14VCC		14VCC
		7	GND					10	8	8
		SN74LVC07A			U19					9	10
						VCC			7 GND
					11	14	10				7 GND
U20	14VCC				7	GND
					SN74LVC07A
13	12										SN74LVC02A
	7 GND							U23		U24
SN74LVC06A								SN74HC03		11	14VCC
					U19			12	14 VCC
						VCC			11		13
					13	14	12	13		12
									7 GND		7 GND
					7
						GND
					SN74LVC07A
U20	14VCC
11	10
	7 GND										A
SN74LVC06A

				TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD				REV:
				DECOUPLING			DRAWN BY:	0.5
					R	PCG PLATFORM DESIGN		PROJECT:
							PCG AE	Camino2
						1900 PRAIRIE CITY ROAD
						FOLSOM, CALIFORNIA 95630	LAST REVISED:	SHEET:
							3-20-2000_10:14	40 OF 40
6	5	4	3			2	1