Intel 820E manual Cable Detection for Ultra ATA/66 and Ultra ATA/100

Intel® 820E Chipset

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2.12.1.Cable Detection for Ultra ATA/66 and Ultra ATA/100

The ICH2 IDE controller supports PIO, multiword (8237-style) DMA, and Ultra DMA modes 0 through

5.The ICH2 must determine the type of cable present, to configure itself for the fastest possible transfer mode that the hardware can support.

An 80-conductor IDE cable is required for Ultra ATA/66 and Ultra ATA/100. This cable uses the same 40-pin connector as the old 40-pin IDE cable. The wires in the cable alternate as follows: ground, signal, ground, signal, ground, signal, ground…. All ground wires are tied together on the cable (and they are

tied to ground on the motherboard through the ground pins in the 40-pin connector). This cable conforms to the Small Form Factor Specification SFF-8049, which is obtainable from the Small Form Factor Committee.

To determine if the ATA/66 or ATA/100 mode can be enabled, the Intel 820E chipset requires that the system software attempt to determine the type of cable used in the system. If the system software detects an 80-conductor cable, it may use any Ultra DMA mode up to the highest transfer mode supported by both the chipset and the IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33).

Intel recommends that cable detection be performed using a combination host-side/device-side detection mechanism. Note that host-side detection cannot be implemented on an NLX form factor system, since this configuration does not define the interconnect pins for the PDIAG#/CBLID# from the riser (containing the ATA connectors) to the motherboard. These systems must rely only on the device-side detection mechanism.

2.12.2.Combination Host-Side/Device-Side Cable Detection

Host-side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of two GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in the following figure. All IDE devices have a 10 kΩ pull-up resistor to 5 V on this signal. Not all GPI and GPIO pins on the ICH2 are 5 V tolerant. If non-5 V tolerant inputs are used, a resistor divider is required to prevent 5 V on the ICH2 or FWH Flash BIOS pins. The proper value of the divider resistor is 10 kΩ , as shown in Figure 46.

80 Design Guide