Intel® 820E Chipset
R
Design Guide 5
2.22. LAN Layout Guidelines................................................................................................ 102
2.22.1. ICH2 – LAN Interconnect Guidelines ........................................................103
2.22.1.1. Bus Topologies............................................................................. 104
2.22.1.2. Point-to-Point Interconnect........................................................... 104
2.22.1.3. LOM/CNR Interconnect................................................................ 104
2.22.1.4. Signal Routing and Layout............................................................105
2.22.1.5. Crosstalk Consideration ...............................................................106
2.22.1.6. Impedances.................................................................................. 106
2.22.1.7. Line Termination........................................................................... 106
2.22.2. General LAN Routing Guidelines and Considerations.............................. 107
2.22.2.1. General Trace Routing Considerations........................................ 107
2.22.2.1.1. Trace Geometry and Length....................................... 108
2.22.2.1.2. Signal Isolation........................................................... 108
2.22.2.2. Power and Ground Connections ..................................................108
2.22.2.2.1. General Power and Ground Plane Considerations ....108
2.22.2.3. 4-Layer Board Design................................................................... 110
2.22.3. Intel® 82562EH Home/PNA* Guidelines ...................................................112
2.22.3.1. Power and Ground Connections ..................................................112
2.22.3.2. Guidelines for Intel® 82562EH Component Placement ................112
2.22.3.3. Crystals and Oscillators................................................................ 112
2.22.3.4. Phoneline HPNA Termination....................................................... 113
2.22.3.5. Critical Dimensions....................................................................... 114
2.22.3.5.1. Distance from Magnetics Module to Line RJ11.......... 114
2.22.3.5.2. Distance from Intel® 82562EH Component to
Magnetics Module ......................................................114
2.22.3.5.3. Distance from LPF to Phone RJ11............................. 115
2.22.4. Intel® 82562ET / Intel® 82562EM Component Guidelines......................... 115
2.22.4.1. Guidelines for Intel® 82562ET / Intel® 82562EM Component
Placement .................................................................................... 115
2.22.4.2. Crystals and Oscillators................................................................ 116
2.22.4.3. Intel® 82562ET / Intel® 82562EM Component Termination
Resistors ....................................................................................116
2.22.4.4. Critical Dimensions....................................................................... 116
2.22.4.4.1. Distance from Magnetics Module to RJ45.................. 117
2.22.4.4.2. Distance from the Intel® 82562ET Component to the
Magnetics Module ......................................................118
2.22.4.5. Reducing Circuit Inductance......................................................... 118
2.22.4.6. Terminating Unused Connections................................................ 118
2.22.4.6.1. Termination Plane Capacitance .................................118
2.22.5. Intel® 82562ET/EM Disable Guidelines....................................................... 119
2.22.6. Intel® 82562ET and Intel® 82562EH Components’ Dual-Footprint
Guidelines.................................................................................................... 120
2.22.7. ICH2 Decoupling Recommendations........................................................ 122
2.23. FWH Flash BIOS Guidelines....................................................................................... 124
2.23.1. In-Circuit FWH Flash BIOS Programming ................................................ 124
2.23.2. FWH Flash BIOS VPP Design Guidelines ................................................124
2.24. ICH2 Design Checklist ................................................................................................125
2.25. ICH2 Layout Checklist................................................................................................. 134
3. Advanced System Bus Design................................................................................................. 139
3.1. Terminology and Definitions........................................................................................ 139
3.2. AGTL+ Design Guidelines........................................................................................... 141
3.2.1. Initial Timing Analysis................................................................................ 142
3.2.2. Determine the Desired General Topology, Layout, and Routing............... 145