Intel 820E manual Reducing Circuit Inductance, Terminating Unused Connections

Intel® 820E Chipset

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2.22.4.4.2.Distance from the Intel® 82562ET Component to the Magnetics Module

Distance ‘B’ in Figure 73 also should be designed to be less than 1 inch between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be observed closely. Generally speaking, any trace section intended for use with high-speed signals should comply with proper termination practices. Proper signal termination can reduce reflections caused by impedance mismatches between a device and the traces. Reflected signals may have a high- frequency component that may contribute more EMI than the original signal itself. For this reason, these traces should be designed with a 100 Ω differential value. These traces also should be symmetric and of equal length within each differential pair.

2.22.4.5.Reducing Circuit Inductance

The following guidelines explain how to reduce circuit inductance in both backplanes and motherboards. Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas on a ground or power plane, the signal conductors should not cross them. This increases inductance and associated radiated-noise levels. To reduce coupling, noisy logic grounds should be separated from analog signal grounds. Noisy logic grounds sometimes can affect sensitive DC subsystems, such as analog-to-digital conversion, operational amplifiers, etc. All ground vias should be connected to every ground plane. Similarly, every power via should be connected to all power planes at equal potential. This helps reduce circuit inductance. It also is recommended to physically locate grounds so as to minimize the loop area between a signal path and its return path. Rise and fall times should be as slow as possible. Because signals with fast rise and fall times contain many high-frequency harmonics, significant radiation can result. The most-sensitive signal returns closest to the chassis ground should be connected. This results in a smaller loop area and reduces the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software.

2.22.4.6.Terminating Unused Connections

In Ethernet designs, it is common practice to terminate unused connections on the RJ-45 connector and the magnetics module to ground. Depending on overall shielding and grounding design, grounding may be to the chassis ground, signal ground or a termination plane. Care must be taken when using various grounding methods, to insure that emission requirements are met. The method most often implemented is use of a floating termination plane, which is cut out of a power plane layer. This floating plane acts as a plate of a capacitor with an adjacent ground plane. The signals can be routed through 75 Ω resistors to the plane. The stray energy on unused pins is then carried to the plane.

2.22.4.6.1. Termination Plane Capacitance

The recommended minimum termination plane capacitance is 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN), from the unused pairs of the RJ45. Pads may be placed for additional capacitance to chassis ground, which may be required if the termplane capacitance is not high enough to pass EFT (Electrical Fast Transient) testing. To meet EFT requirements, used discrete capacitors should be rated at 1000 VAC minimum.

118 Design Guide