Intel 820E manual Design Guide

Intel® 820E Chipset

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Term	Definition
Flight time	Flight time is a timing equation term that includes the signal propagation delay, any
	effects of the system on the TCO of the driver, plus any adjustments to the signal at
	the receiver needed to guarantee the setup time of the receiver.
	More precisely, flight time is defined as the time difference between a signal at the
	input pin of a receiving agent crossing VREF (adjusted to meet the receiver
	manufacturer’s conditions required for AC timing specifications; i.e., ringback,
	etc.) and the output pin of the driving agent crossing VREF, if the driver was driving
	the test load used to specify the driver’s AC timings.
	The VREF guard band takes into account sources of noise that may affect the way an
	AGTL+ signal becomes valid at the receiver. See the definition of the VREF guard
	band.
	Maximum and Minimum Flight Time. Flight time variations can be caused by
	many different parameters. Obvious causes include variation of the board dielectric
	constant, changes in the load condition, crosstalk, VTT noise, VREF noise, variation
	of the termination resistance, and differences in I/O buffer performance as a
	function of temperature, voltage, and the manufacturing process. Less obvious
	causes include the effects of Simultaneous Switching Output (SSO) and packaging
	effects.
	Maximum Flight Time is the largest flight time a network will experience under
	all variations of conditions. Maximum flight time is measured at the appropriate
	VREF guard-band boundary.
	Minimum Flight Time is the smallest flight time a network will experience under
	all variations of conditions. Minimum flight time is measured at the appropriate
	VREF guard-band boundary.
GTL+	GTL+, the bus technology used by the Pentium® Pro processor, is an incident wave
	switching, open-drain bus with pull-up resistors that provide both the high logic
	level and termination. It is an enhancement of GTL (Gunning Transceiver Logic)
	technology.
Network	Trace of a printed circuit board (PCB) that completes an electrical connection
	between two or more components
Network length	Distance between extreme bus agents on the network. It does not include the
	distance of the connection between the end bus agents and the termination resistors.
Overdrive	Voltage range, at a receiver, located above and below VREF for signal integrity
region	analysis.
Overshoot	Maximum voltage allowed for a signal at the processor core pad. See each
	processor’s datasheet for the overshoot specification.
Pad	A feature of a semiconductor die contained within an internal logic package used to
	connect the die to the package bond wires. A pad is only observable in simulation.
Pin	A feature of a logic package used to connect the package to an internal substrate
	trace
Ringback	Voltage that a signal rings back to after achieving its maximum absolute value.
	Ringback may be due to reflections, driver oscillations, etc. See the respective
	processor’s datasheet for the ringback specification.
Settling limit	Defines the maximum amount of ringing at the receiving pin that a signal must
	reach before its next transition. See the respective processor’s datasheet for the
	settling limit specification.
Setup window	Time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid
	clock edge. This window may differ for each type of bus agent in the system.

140 Design Guide