Design Guide | Intel 820E specs

Intel® 820E Chipset

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138	Design Guide

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Intel 820E manual Design Guide

Contents

Intel 820E Chipset Design Guide Intel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Tables Mil Stack-Up 135 Revision History Rev Description Date Introduction About This Design Guide Reference Documents System Overview Chipset Components Memory Controller Hub MCHController Hub 2 ICH2 ISA Bridge FWH Flash BiosBandwidth Summary Intel 820E Chipset Platform Bandwidth Summary System Configuration MCH UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs Streaming Simd Extensions Platform InitiativesDirect Rambus RAM Rdram AGP Expanded USB Support Integrated LAN ControllerUltra ATA/100 Support Manageability SMBus Function DisableIntruder Detect Interrupt Controller 9. AC’97 C AC’97 Connections Ebga Low-Pin-Count LPC Interface This page is intentionally left blank General Recommendations Component Quadrant Layout MCH Intel 820E Chipset Component Placement Sample ATX and NLX MCH/ICH2 Component Placement Core Chipset Routing Recommendations Primary-Side MCH Core Routing Example ATX Secondary-Side MCH Core Routing Example ATX Source-Synchronous Strobing Data Strobing Example AGP 2× Data/Strobe Association Differential Clocking/StrobingDirect RDRAM* Interface Data Associated Strobe Stack-Up Direct RDRAM* Layout Guidelines Placement Guidelines for Motherboard Routing Lengths RSL RoutingReference Trace Description Maximum Trace Length RSL Routing Diagram Secondary-Side RSL Breakout Example RSL Termination Direct Rdram Termination Direct RDRAM* Ground Plane Reference Direct RDRAM* Termination Example Plane GND Plane Direct RDRAM* Connector Compensation Equation 1. Approximate Copper Tab Area Calculation Copper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer RSL and Clocking Signal Routing Layer Capacitance pF Section B See Note, Bottom Layer Flood Signal RSL Signal Layer Alternation Length Matching Methods RSL Routing Layer Requirements Equation 2. Rdram RSL Signal Trace Length Calculation Equation 3. Rdram Clock Signal Trace Length Calculation Via Compensation Length Matching and Via Compensation Example Signal Ball on Nominal Package Direct RDRAM* Reference Voltage High-Speed Cmos Routing SIO Routing High-Speed Cmos Termination Suspend-to-RAM Shunt Transistor Rdram Cmos Shunt Transistor RSL Signals High-Speed Serial Clocks Direct RDRAM* Design ChecklistSignal List Direct RDRAM* Clock Routing Intel 820E Chipset If Signal Routed from MCH Primary side AGP Interface Signal Groups AGP Signal Groups Interfaces 6 Inches 2 × Timing Domain Routing Guidelines3 ×/4× Timing Domain Routing Guidelines AGP 2.0 Data/Strobe Associations Interfaces 6 Inches and 7.25 Inches AGP 2×/4× Routing Example for Interfaces 6 Inches All AGP Interfaces Signal Maximum Trace Spacing Length Relative ToAGP 2.0 Routing Summary AGP 2.0 Routing Summary1,2 Recommendations AGP Clock RoutingGeneral AGP Routing Guidelines Decoupling Vddq Generation and TYPEDET# Ground Reference TYPDET#/VDDQ Relationship TYPEDET# on Add-in Card DDQ Supplied by MB Vref Generation for AGP 2.0 2× and 4× AGP Vddq Generation Example Circuit AGP 2.0 Vref Generation and Distribution Compensation AGP Pull-Ups16 k Ω Connector Universal Connector AGP Signal Voltage Tolerance ListConnector / Add-in Card Interoperability Motherboard / Add-in Card Interoperability AGP Universal Retention Mechanism RM AGP Left-Handed Retention Mechanism AGP Left-Handed RM Keep-Out Information AMP P/N Hub Interface Signal Routing Example Hub Interface Bit Hub Interface Buffer Configuration Setting Bit Hub Interface Data SignalsBit Hub Interface Strobe Signals Bit Hub Interface Routing Guidelines Bit Hub Interface Hubref Generation Circuit Specifications MCH ICH2 Hlrefa Hubref Bit Hub Interface Rcomp Resistor Values Bit Hub Interface CompensationBit Hub Interface Decoupling Guidelines Component Hub Interface Trace Rcomp Resistor Value Additional Host Bus Guidelines System Bus Ground Plane ReferenceMinimizing Crosstalk on the AGTL+ Interface IDE Interface Additional ConsiderationsCable Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side Cable Detection Combination Host-Side/Device-Side IDE Cable Detection Device-Side Cable Detection Device-Side IDE Cable Detection Primary IDE Connector Requirements Secondary IDE Connector Requirements SDCS1# SDCS3# SDIOR# SDIOW# SddreqSiordy IRQ15 SDDACK# 13. AC’97 ICH2 AC’97- Codec Connection Intel 820E Chipset Motherboard CNR Board CNR Signal Descriptions AC97RESET#CDCDNENAB# Valid Codec Configurations Valid Codec ConfigurationsCodec Configurations Invalid Codec Configurations 13.3. AC’97 Routing Using Native USB Interface USBMotherboard Implementation Recommended USB trace characteristics ISA SupportDisabling the Native USB Interface of ICH2 16. I/O Apic Design Recommendation SMBus/SMLink Interface Pull-Up Requirements for SMBus and SMLink Signals SMBus / SMLink Use Implementation PCI RTC RTC Crystal External Capacitors RTC External Battery Connection RTC Layout Considerations RTC External Rtcrst Circuit Rtcrst External Circuit for ICH2 RTC Vbias DC Voltage and Noise Measurements Spkr Pin ConsiderationRTC Routing Guidelines RTC-Well Input Strap Requirements Function in ICH2 using the PCI IRQ in Ioapic ICH2 Pirq RoutingUsage of I/O Apic Interrupt Inputs 16 through PIRQA# PIRQB# PIRQC# PIRQD# LAN Connect Component Connection FeaturesLAN Layout Guidelines PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd ICH2 LAN Interconnect Guidelines LAN Design Guide Section ReferenceLayout Section Previous Design Guide Section Bus Topologies Point-to-Point InterconnectLOM/CNR Interconnect Signal Routing and Layout ConfigurationLength Requirements for Figure Crosstalk Consideration ImpedancesLine Termination General LAN Routing Guidelines and Considerations General Trace Routing Considerations Power and Ground Connections Trace Geometry and Length Ground Plane Separation Layer Board Design Design Guide 111 Crystals and Oscillators Guidelines for Intel 82562EH Component PlacementIntel 82562EH Home/PNA* Guidelines Related Documents Phoneline Hpna Termination Intel 82562EH Component Termination Eeprom Critical DimensionsLPF Distance Priority Guideline Intel 82562ET / Intel 82562EM Component Guidelines Distance from LPF to Phone RJ11 Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Reducing Circuit Inductance Terminating Unused Connections Intel 82562ET/EM Disable Guidelines LAN Disable Circuit Lancl Dual-Footprint Analog Interface Power Plane/Pins # Decoupling Capacitor Value ICH2 Decoupling RecommendationsDecoupling Capacitor Recommendation Decoupling Capacitor Layout FWH Flash Bios Guidelines In-Circuit FWH Flash Bios ProgrammingFWH Flash Bios VPP Design Guidelines ICH2 Design Checklist Checklist Items Recommendations Reason/EffectPCI Interface LAN Interface FWH Flash Bios InterfaceHub Interface Eeprom Interface PIRQ#H Interrupt InterfacePIRQ#DA PIRQ#E Gpio USB InterfaceVCCSUS3.3 Processor Signals System Management RTCAC’97 Spkr Miscellaneous SignalsPower 5VREF SUS IDE Checklist ISA Bridge Checklist Checklist ItemsICH2 AD22 / ISA IDE Interface ICH2 Layout ChecklistBit Hub Interface USB LAN Connect I/F ICH2 Decoupling CK-SKS Clocking Layout Recommendations Yes 138 Design Guide Terminology and Definitions Term Definition 140 Design Guide AGTL+ Design Guidelines Guideline Methodology Equation 5. Hold Time Equation 4. Setup TimeInitial Timing Analysis Equation 6. Maximum Flight Time AGTL+ Parameters for Example Calculations1,2 IC Parameters Pentium Intel Example Tfltmax Calculations for 133 MHz Bus1 Driver Receiver Clk Methodology Determine the Desired General Topology, Layout, and RoutingPre-Layout Simulation Sensitivity Analysis Monte Carlo Analysis Simulation Criteria Estimate Component-to-Component Spacing for AGTL+ Signals Place and Route BoardLayout and Route Board Host Clock Routing Apic Data Bus Routing Trace Width Space GuidelinesCrosstalk Type Trace WidthSpace Ratio Intersymbol Interference Post-Layout Simulation Validation Crosstalk AnalysisMeasurements Flight Time Simulation Equation 8. Valid Delay Equation Flight Time Hardware ValidationSET Q CLR Q Theory AGTL+Timing Requirements Crosstalk Theory Aggressor and Victim Networks Potential Termination Crosstalk Problems More Details and Insight Textbook Timing Equations Power Distribution Effective Impedance and Tolerance/Variation One Signal Layer and One Reference Plane Reference Planes and PCB Stack-Up Layer Switch with Multiple Reference Planes Same Type High-Frequency Decoupling One Layer with Multiple Reference Planes Clock Routing Vref Guard Band Ringback LevelsOverdrive Region Conclusion Flight Time Definition and Measurement Clock Generation Intel 820E Chipset Platform System ClocksNumber Name on CK133 Used for Routed to Frequency Voltage Intel 820E Chipset Platform Clock Distribution Intel 820E Chipset Platform Clock Skews Relationship Skew Pin-to-Pin ps Board ps Total ps Min MaxLPCCLK, Pciclk Intel 820E Chipset Clock Routing Guidelines1,2 ±TBD3 Intel 820E Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name Component Component Placement and Interconnection Layout Requirements 1 .318 MHz Crystal to CK1332. CK133 to Drcg MCH-to-DRCG Routing Diagram MCH to Drcg Trace Geometry DRCG-to-RDRAM ChannelTrace Length Clock From Length inches Section Differential Clock Routing Diagram Sections A, C & D Component Nominal Value Drcg Impedance Matching CircuitExternal Drcg Component Values1,2 CMID, CMID2 Series Termination Resistors for CK133 Clock Outputs AGP Clock Routing GuidelinesClock Routing Guidelines for Intel PGA370 Designs Drcg Layout Example Unused Output Termination Unused OutputsDecoupling Recommendation for CK133 and Drcg Buffer Name CC Range Impedance If Unused Output Drcg Frequency Selection Table and Jitter Specification Drcg Frequency Selection and the DRCG+ DRCG+ Frequency Selection Schematic DRCG+ Frequency Selection Stack-Up Requirement PCB Materials Design Process Test Coupon Design Guidelines Stack-Up Examples Recommended Stack-UpInner-Layer Routing Sample SM max Resin % Impedance Calculation Tools Field Solver vs. Zcalc Testing Board Impedance Board Impedance/Stack-up Summary 182 Design Guide Power Delivery Terminology and DefinitionsTerm Definition Intel 820E Chipset Power Delivery Example Dual Switch VCC Vbsy V and 2.5 V Power Sequencing Schottky Diode 3VSB ICH2 1.8 V / 3.3 V Power Sequencing VSB Example 1.8V/3.3V Power Sequencing Circuit 4 .3V/V5REF Sequencing Excessive Power Consumption by 64/72-Mbit Rdram Option 1 Reduce the Clock Frequency During InitializationVref Use a GPO to Reduce Drcg Frequency ICH2 Power Plane Split Example of ICH2 Power Plane Split Intel 820E Chipset Component Thermal Design Power Thermal Design PowerFeatures Component Thermal Design Power 133/400 MHz Glue Chip Vendors Vendor Intel Contact Contact Information Appendix a Reference Design Schematics Uniprocessor Reference Design Feature Set 196 Design Guide Prairie City Road REVDrawn by PCG Platform Design Project PCG AE FOLSOM, California Last Revised Sheet Block Diagram Device Table AN9 AK8AH8 AL9 Gtlref CPURST#R2 DBRESET#VCMOS15 Tckr TDI Tmsr Clock Synthesizer Connagpref Hubref RamrefrRamref Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host GAD1 GAD2 GAD0GAD0 GAD1 GAD2 GAD3 AD2 AD0AD1 AD3 Vbatcr 1UF ACRESET#CR4 Rtcrstjp NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 NC1 GndaFwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36 VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 TERMDQA80 SWP RSRV4/RESETRSRV4/RESET SWP Rimm LDQA0 Super I/O AC’97 Audio Micinc Micinr MicinfbMicin DB15AUDSTK Communication And Network Riser CNR RP7 Stubs on AC97 LinkACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2 ACSDATAIN0CNR Acsynccnr Acsdataoutcnr LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH LAN RJ45 For 82562ET/EM H1138ARAGONITELanactled R381LANCLKX2 25MHZY5 Xtal Y2 Xtal LANCLKX1 LAN Option Intel PART# Stuff for 82562EH SW1 Power SWPower LED VCC12 Irtx USBAGP+ B4 Usbagp AGP4XU20 AGPOC#TYPEDET# Agpclkconn B7 CLK Ptms VCC5 VCC12PCI3CON PTRST# Ptck Ptdi PCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy Game Port VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr Vccvid REV Project VRM Fault VRM IFBFAULT# IFB Imax VRM G1 VRM G2 Voltage Regulators VCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH 1UF-X7RVCC33SBYTG VCC33SBYSW VCC25SBY SBY ITH R Power Connector BPRI# DBSY# HREQ#0 PCI/AGP Pullups/Pulldowns Rambus* Termination Termcmd Termsck Decoupling VCMOS18SBY Bulk Decoupling Drawn by PCG Platform Design Project PCG AE Revision History Revision History Drawn by PCG Platform Design Project PCG AE TESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB# Hub Interface Connector For debug onlyProbe Connector HL8 HL4 HL5 HL6 HL7