Intel 820E 2.7.2.1. RSL Routing

Intel® 820E Chipset
R
Design Guide 35
2.7.2.1. RSL Routing
The RSL signals enter the first RIMM on the left side, propa gate through the RIMM, and exit on the
right. The signal continues through the rest of the existing RIMMs until it is terminated at VTERM. All
unpopulated slots must have continuity modules in place to ensure that the signals propagate to the
termination.
Figure 13. RSL Routing Dimensions
rsl_route
MCH
MCH to first
RIMM
RIMM_0 RIMM_1
A B C
RIMM to
RIMM
RIMM to
Termination
0"-3.50" 0.4"-0.45" 0"-3"
To maintain a nominal 28 Ω trace impedance, the RSL signals must be 18 mils wide. To control crosstalk
and odd/even-mode velocity deltas, there must be a 10 mil ground isolation trace routed between
adjacent RSL signals. The 10 mil ground isolation traces must be connected to ground with a via every 1
inch. A 6 mil gap is required between the RSL signals and the ground isolation trace. These signals must
be length-matched to ±10 mils in line section A and to ±2 mils in line section B, using the trace length
matching methods in Section 2.7.2.6. To ensure uniform trace lines, trace width variation must be
uniform on all RSL signals at every neckdown for each line section. All RSL signals must have the same
number of vias. It may be necessary to place vias on RSL signals where they are not necessary to meet
this via loading requirement (i.e., dummy vias).
Table 3. Placement Guidelines for Motherboard Routing Lengths
Reference Trace Description Maximum Trace Length (in.)
A MCH to first RIMM connector 0 to 3.50
B RIMM to RIMM 0.4 to 0.45
C RIMM to termination 0 to 3