Intel 820E manual Power and Ground Connections, Trace Geometry and Length

Intel® 820E Chipset

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2.22.2.1.1. Trace Geometry and Length

The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane. To minimize trace inductance, high-speed signals and signal layers close to a ground or power plane should be as short and wide as practical. Ideally, this ratio of trace width to height above ground plane should be between 1:1 and 3:1. To maintain trace impedance, the trace width should be modified when changing from one board layer to another, if the two layers are not equidistant from the power or ground plane. Differential trace impedances should be controlled at approximately

100 Ω . It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by 10 Ω , when the traces within a pair are closer than 0.030 inch (edge to edge).

Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long-and- thin traces are more inductive and would reduce the intended effect of decoupling capacitors. For similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the decoupling capacitors should be sufficiently large in diameter to decrease series inductance.

2.22.2.1.2. Signal Isolation

Signal isolation rules include the following:

•If possible, separate and group signals by function on separate layers. Maintain a gap of 100 mils between all differential pairs (phone line and Ethernet) and other nets, but group associated differential pairs. Note: Over the length of a trace run, each differential pair should be at least 0.3 inch from any parallel signal trace.

•Physically group all components associated with one clock trace, to reduce the trace length and radiation.

•Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals.

•Avoid routing high-speed LAN or phone line traces near other high-frequency signals associated with a video controller, cache controller, processor or similar device.

2.22.2.2.Power and Ground Connections

Rules and guidelines for power and ground connections include the following:

•All VCC pins should be connected to the same power supply.

•All VSS pins should be connected to the same ground plane.

•Four to six decoupling capacitors, including two 4.7 µF capacitors are recommended.

•Place decoupling as close as possible to power pins.

2.22.2.2.1. General Power and Ground Plane Considerations

To properly implement the common-mode choke functionality of the magnetics module, the chassis or output ground (secondary side of transformer) should be physically separated from the digital or input ground (primary side) by at least 100 mils.

108 Design Guide