NC1 Gnda, VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 | Intel 820E

8

7

6

5

4

3

2

1

FWH

VCC3_3

D

D

C301

C298

C297

C308

VCC3_3

VCC3_3

0.1UF

0.1UF

0.1UF

0.1UF

Do not tie Vpp to 12V. Vpp should be tied

to VCC3_3 for onboard programming.

U16

C300

C305

R296

1

NC1

GNDA

40

0.1UF

0.1UF

FWH_IC

2

39

IC

VCCA

8.2K

3

38

LFRAME#/FWH4

9,12

NC3

FWH4

4

NC4

INIT#

37

HINIT#

4,8

5

FWH

36

NC5

RFU36

6

35

R298

NC6

RFU35

FGPI4

7

34

FGPI4

RFU34

8.2K

8

33

NC8

RFU33

C

FWHPCLK

9

32

5

CLK

RFU32

C

10

31

R299

VCC10

VCC31

VPP_R

11

30

VPP

GND30

0K

PCIRST#

12

29

RST#

GND29

6,8,11,12,24,25,26,27

13

28

LAD3/FWH3

NC13

FWH3

9,12

14

27

LAD2/FWH2

R300

NC14

FWH2

9,12

FGPI3

15

26

LAD1/FWH1

R303

FGPI3

FWH1

9,12

8.2K

FGPI2

16

25

LAD0/FWH0

R305

FGPI2

FWH0

9,12

27

S100DETECT

8.2K

FGPI1

17

24

R306

FGPI1

ID0

P100DETECT

0K

FGPI0

18

23

FGPI0

ID1

27

0K

19

22

WP#

ID2

20

21

TBL#

ID3

For drive side detection, stuff R304,R307. No stuff R305,R306.

R304

10K

R307

VCC3_3

For host side detection, stuff R304,R305,R306,R307.

10K

VCC3_3

R308

WPROT

4.7K

B

JP21

B

Top Block Lock

TBLK_LCK

4.7K

R310

A

A

TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD					REV:
FWH				DRAWN BY:	0.5
		R	PCG PLATFORM DESIGN	DRAWN BY:	PROJECT:
		R	PCG PLATFORM DESIGN	PCG AE	Camino2
			1900 PRAIRIE CITY ROAD	PCG AE	Camino2
			FOLSOM, CALIFORNIA 95630	LAST REVISED:	SHEET:
			FOLSOM, CALIFORNIA 95630	3-20-2000_10:15	10 OF 40
				3-20-2000_10:15	10 OF 40

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Image 206

Intel 820E NC1 Gnda, Fwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36, VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29

Contents

Intel 820E Chipset Design Guide Intel 820E Chipset Contents 1.1 102 AGTL+ 191 Figures CDCDNENAB# Support Circuitry for Multi-Channel Audio Upgrade Tables Mil Stack-Up 135 Revision History Rev Description Date Introduction About This Design Guide Reference Documents System Overview Controller Hub 2 ICH2 Chipset ComponentsMemory Controller Hub MCH ISA Bridge FWH Flash BiosBandwidth Summary Intel 820E Chipset Platform Bandwidth Summary System Configuration MCH UltraATA/100/66/33 USB Ports 2 HC AC97 Codecs Streaming Simd Extensions Platform InitiativesDirect Rambus RAM Rdram AGP Expanded USB Support Integrated LAN ControllerUltra ATA/100 Support Manageability SMBus Function DisableIntruder Detect Interrupt Controller 9. AC’97 C AC’97 Connections Ebga Low-Pin-Count LPC Interface This page is intentionally left blank General Recommendations Component Quadrant Layout MCH Intel 820E Chipset Component Placement Sample ATX and NLX MCH/ICH2 Component Placement Core Chipset Routing Recommendations Primary-Side MCH Core Routing Example ATX Secondary-Side MCH Core Routing Example ATX Source-Synchronous Strobing Data Strobing Example AGP 2× Data/Strobe Association Differential Clocking/StrobingDirect RDRAM* Interface Data Associated Strobe Stack-Up Direct RDRAM* Layout Guidelines Reference Trace Description Maximum Trace Length Placement Guidelines for Motherboard Routing LengthsRSL Routing RSL Routing Diagram Secondary-Side RSL Breakout Example RSL Termination Direct Rdram Termination Direct RDRAM* Ground Plane Reference Direct RDRAM* Termination Example Plane GND Plane Direct RDRAM* Connector Compensation Equation 1. Approximate Copper Tab Area Calculation Copper Tab Area Calculation Connector Compensation Example Section a See Note, Top Layer Section a See Note, Bottom Layer Section B See Note, Top Layer RSL and Clocking Signal Routing Layer Capacitance pF Section B See Note, Bottom Layer Flood Signal RSL Signal Layer Alternation Length Matching Methods RSL Routing Layer Requirements Equation 2. Rdram RSL Signal Trace Length Calculation Equation 3. Rdram Clock Signal Trace Length Calculation Via Compensation Length Matching and Via Compensation Example Signal Ball on Nominal Package Direct RDRAM* Reference Voltage High-Speed Cmos Routing SIO Routing High-Speed Cmos Termination Suspend-to-RAM Shunt Transistor Rdram Cmos Shunt Transistor RSL Signals High-Speed Serial Clocks Direct RDRAM* Design ChecklistSignal List Direct RDRAM* Clock Routing Intel 820E Chipset If Signal Routed from MCH Primary side AGP Interface Signal Groups AGP Signal Groups Interfaces 6 Inches 2 × Timing Domain Routing Guidelines3 ×/4× Timing Domain Routing Guidelines AGP 2.0 Data/Strobe Associations Interfaces 6 Inches and 7.25 Inches AGP 2×/4× Routing Example for Interfaces 6 Inches All AGP Interfaces Signal Maximum Trace Spacing Length Relative ToAGP 2.0 Routing Summary AGP 2.0 Routing Summary1,2 Recommendations AGP Clock RoutingGeneral AGP Routing Guidelines Decoupling Vddq Generation and TYPEDET# Ground Reference TYPDET#/VDDQ Relationship TYPEDET# on Add-in Card DDQ Supplied by MB Vref Generation for AGP 2.0 2× and 4× AGP Vddq Generation Example Circuit AGP 2.0 Vref Generation and Distribution 16 k Ω CompensationAGP Pull-Ups Connector Universal Connector AGP Signal Voltage Tolerance ListConnector / Add-in Card Interoperability Motherboard / Add-in Card Interoperability AGP Universal Retention Mechanism RM AGP Left-Handed Retention Mechanism AGP Left-Handed RM Keep-Out Information AMP P/N Hub Interface Signal Routing Example Hub Interface Bit Hub Interface Buffer Configuration Setting Bit Hub Interface Data SignalsBit Hub Interface Strobe Signals Bit Hub Interface Routing Guidelines Bit Hub Interface Hubref Generation Circuit Specifications MCH ICH2 Hlrefa Hubref Bit Hub Interface Rcomp Resistor Values Bit Hub Interface CompensationBit Hub Interface Decoupling Guidelines Component Hub Interface Trace Rcomp Resistor Value Minimizing Crosstalk on the AGTL+ Interface Additional Host Bus GuidelinesSystem Bus Ground Plane Reference Cable IDE InterfaceAdditional Considerations Cable Detection for Ultra ATA/66 and Ultra ATA/100 Combination Host-Side/Device-Side Cable Detection Combination Host-Side/Device-Side IDE Cable Detection Device-Side Cable Detection Device-Side IDE Cable Detection Primary IDE Connector Requirements Siordy IRQ15 SDDACK# Secondary IDE Connector RequirementsSDCS1# SDCS3# SDIOR# SDIOW# Sddreq 13. AC’97 ICH2 AC’97- Codec Connection Intel 820E Chipset Motherboard CNR Board CNR CDCDNENAB# Signal DescriptionsAC97RESET# Valid Codec Configurations Valid Codec ConfigurationsCodec Configurations Invalid Codec Configurations 13.3. AC’97 Routing Motherboard Implementation Using Native USB InterfaceUSB Disabling the Native USB Interface of ICH2 Recommended USB trace characteristicsISA Support 16. I/O Apic Design Recommendation SMBus/SMLink Interface Pull-Up Requirements for SMBus and SMLink Signals SMBus / SMLink Use Implementation PCI RTC RTC Crystal External Capacitors RTC External Battery Connection RTC Layout Considerations RTC External Rtcrst Circuit Rtcrst External Circuit for ICH2 RTC Vbias DC Voltage and Noise Measurements Spkr Pin ConsiderationRTC Routing Guidelines RTC-Well Input Strap Requirements Usage of I/O Apic Interrupt Inputs 16 through Function in ICH2 using the PCI IRQ in IoapicICH2 Pirq Routing PIRQA# PIRQB# PIRQC# PIRQD# LAN Connect Component Connection FeaturesLAN Layout Guidelines PIRQE# PIRQF# PIRQG# PIRQH# Inta Intb Intc Intd Layout Section Previous Design Guide Section ICH2 LAN Interconnect GuidelinesLAN Design Guide Section Reference LOM/CNR Interconnect Bus TopologiesPoint-to-Point Interconnect Length Requirements for Figure Signal Routing and LayoutConfiguration Line Termination Crosstalk ConsiderationImpedances General LAN Routing Guidelines and Considerations General Trace Routing Considerations Power and Ground Connections Trace Geometry and Length Ground Plane Separation Layer Board Design Design Guide 111 Crystals and Oscillators Guidelines for Intel 82562EH Component PlacementIntel 82562EH Home/PNA* Guidelines Related Documents Phoneline Hpna Termination Intel 82562EH Component Termination Eeprom Critical DimensionsLPF Distance Priority Guideline Intel 82562ET / Intel 82562EM Component Guidelines Distance from LPF to Phone RJ11 Intel 82562ET/82562EM Component Termination Distance from Magnetics Module to RJ45 Reducing Circuit Inductance Terminating Unused Connections Intel 82562ET/EM Disable Guidelines LAN Disable Circuit Lancl Dual-Footprint Analog Interface Decoupling Capacitor Recommendation Power Plane/Pins # Decoupling Capacitor ValueICH2 Decoupling Recommendations Decoupling Capacitor Layout FWH Flash Bios VPP Design Guidelines FWH Flash Bios GuidelinesIn-Circuit FWH Flash Bios Programming PCI Interface ICH2 Design ChecklistChecklist Items Recommendations Reason/Effect LAN Interface FWH Flash Bios InterfaceHub Interface Eeprom Interface PIRQ#H Interrupt InterfacePIRQ#DA PIRQ#E VCCSUS3.3 GpioUSB Interface Processor Signals AC’97 System ManagementRTC Spkr Miscellaneous SignalsPower 5VREF SUS IDE Checklist ICH2 AD22 / ISA ISA Bridge ChecklistChecklist Items IDE Interface ICH2 Layout ChecklistBit Hub Interface USB LAN Connect I/F ICH2 Decoupling CK-SKS Clocking Layout Recommendations Yes 138 Design Guide Terminology and Definitions Term Definition 140 Design Guide AGTL+ Design Guidelines Guideline Methodology Equation 5. Hold Time Equation 4. Setup TimeInitial Timing Analysis Equation 6. Maximum Flight Time AGTL+ Parameters for Example Calculations1,2 IC Parameters Pentium Intel Example Tfltmax Calculations for 133 MHz Bus1 Driver Receiver Clk Methodology Determine the Desired General Topology, Layout, and RoutingPre-Layout Simulation Sensitivity Analysis Monte Carlo Analysis Simulation Criteria Layout and Route Board Estimate Component-to-Component Spacing for AGTL+ SignalsPlace and Route Board Crosstalk Type Trace WidthSpace Ratio Host Clock Routing Apic Data Bus RoutingTrace Width Space Guidelines Intersymbol Interference Post-Layout Simulation Measurements Flight Time Simulation ValidationCrosstalk Analysis SET Q CLR Q Equation 8. Valid Delay EquationFlight Time Hardware Validation Timing Requirements TheoryAGTL+ Crosstalk Theory Aggressor and Victim Networks Potential Termination Crosstalk Problems More Details and Insight Textbook Timing Equations Power Distribution Effective Impedance and Tolerance/Variation One Signal Layer and One Reference Plane Reference Planes and PCB Stack-Up Layer Switch with Multiple Reference Planes Same Type High-Frequency Decoupling One Layer with Multiple Reference Planes Clock Routing Overdrive Region Vref Guard BandRingback Levels Conclusion Flight Time Definition and Measurement Number Name on CK133 Used for Routed to Frequency Voltage Clock GenerationIntel 820E Chipset Platform System Clocks Intel 820E Chipset Platform Clock Distribution LPCCLK, Pciclk Intel 820E Chipset Platform Clock SkewsRelationship Skew Pin-to-Pin ps Board ps Total ps Min Max Intel 820E Chipset Clock Routing Guidelines1,2 ±TBD3 Intel 820E Chipset Platform System Clock Cross-Reference CK133/DRCG Pin Name Component 2. CK133 to Drcg Component Placement and Interconnection Layout Requirements1 .318 MHz Crystal to CK133 MCH-to-DRCG Routing Diagram MCH to Drcg Trace Geometry DRCG-to-RDRAM ChannelTrace Length Clock From Length inches Section Differential Clock Routing Diagram Sections A, C & D Component Nominal Value Drcg Impedance Matching CircuitExternal Drcg Component Values1,2 CMID, CMID2 Series Termination Resistors for CK133 Clock Outputs AGP Clock Routing GuidelinesClock Routing Guidelines for Intel PGA370 Designs Drcg Layout Example Unused Output Termination Unused OutputsDecoupling Recommendation for CK133 and Drcg Buffer Name CC Range Impedance If Unused Output Drcg Frequency Selection Table and Jitter Specification Drcg Frequency Selection and the DRCG+ DRCG+ Frequency Selection Schematic DRCG+ Frequency Selection Stack-Up Requirement PCB Materials Design Process Test Coupon Design Guidelines Stack-Up Examples Recommended Stack-UpInner-Layer Routing Sample SM max Resin % Impedance Calculation Tools Field Solver vs. Zcalc Testing Board Impedance Board Impedance/Stack-up Summary 182 Design Guide Term Definition Power DeliveryTerminology and Definitions Intel 820E Chipset Power Delivery Example Dual Switch VCC Vbsy V and 2.5 V Power Sequencing Schottky Diode 3VSB ICH2 1.8 V / 3.3 V Power Sequencing VSB Example 1.8V/3.3V Power Sequencing Circuit 4 .3V/V5REF Sequencing Vref Excessive Power Consumption by 64/72-Mbit RdramOption 1 Reduce the Clock Frequency During Initialization Use a GPO to Reduce Drcg Frequency ICH2 Power Plane Split Example of ICH2 Power Plane Split Intel 820E Chipset Component Thermal Design Power Thermal Design PowerFeatures Component Thermal Design Power 133/400 MHz Glue Chip Vendors Vendor Intel Contact Contact Information Appendix a Reference Design Schematics Uniprocessor Reference Design Feature Set 196 Design Guide Prairie City Road REVDrawn by PCG Platform Design Project PCG AE FOLSOM, California Last Revised Sheet Block Diagram Device Table AN9 AK8AH8 AL9 Gtlref CPURST#R2 DBRESET#VCMOS15 Tckr TDI Tmsr Clock Synthesizer Connagpref Hubref RamrefrRamref Hubref Agpref Ramrefb Ramrefa Gtlrefb Gtlrefa Host GAD1 GAD2 GAD0GAD0 GAD1 GAD2 GAD3 AD2 AD0AD1 AD3 Vbatcr 1UF ACRESET#CR4 Rtcrstjp NC6 RFU35 FGPI4 RFU34 NC8 RFU33 Fwhpclk CLK RFU32 NC1 GndaFwhic Vcca LFRAME#/FWH4 NC3 NC4 INIT# HINIT# NC5 RFU36 VCC10 VCC31 Vppr VPP GND30 PCIRST# GND29 TERMDQA80 SWP RSRV4/RESETRSRV4/RESET SWP Rimm LDQA0 Super I/O AC’97 Audio Micinc Micinr MicinfbMicin DB15AUDSTK Communication And Network Riser CNR RP7 Stubs on AC97 LinkACSDATAIN0ICH2 ACSYNCICH2 ACSDATAOUTICH2 ACSDATAIN0CNR Acsynccnr Acsdataoutcnr LAN 82562EH 82562ET/EM LAN RJ11 For 82562EH Lanactled LAN RJ45 For 82562ET/EMH1138ARAGONITE R381LANCLKX2 25MHZY5 Xtal Y2 Xtal LANCLKX1 LAN Option Intel PART# Stuff for 82562EH SW1 Power SWPower LED VCC12 Irtx USBAGP+ B4 Usbagp AGP4XU20 AGPOC#TYPEDET# Agpclkconn B7 CLK Ptms VCC5 VCC12PCI3CON PTRST# Ptck Ptdi PCI Connectors IDE Connectors USB Connectors Port Parallel Serial Ports Keyboard/Mouse/Floppy Game Port VCC5 JOY1XR JOY2XR Midioutr JOY2YR JOY1YR Midiinr Vccvid REV Project VRM Fault VRM IFBFAULT# IFB Imax VRM G1 VRM G2 Voltage Regulators VCC5DUAL VCC33SBY VCC33SBYCOSC VCC33SBYRUN VCC33SBYITH 1UF-X7RVCC33SBYTG VCC33SBYSW VCC25SBY SBY ITH R Power Connector BPRI# DBSY# HREQ#0 PCI/AGP Pullups/Pulldowns Rambus* Termination Termcmd Termsck Decoupling VCMOS18SBY Bulk Decoupling Drawn by PCG Platform Design Project PCG AE Revision History Revision History Drawn by PCG Platform Design Project PCG AE TESTCLK66 HL0 HL1 HL2 HL3 HL9 Hlstb HLSTB# Hub Interface Connector For debug onlyProbe Connector HL8 HL4 HL5 HL6 HL7