Intel 820E manual Gpio, USB Interface, VCCSUS3.3

Intel® 820E Chipset

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Table 32. GPIO

Checklist Items	Recommendations	Reason/Effect
GPIO pins	GPIO[0:7]:	Ensure that all unconnected
	• These pins are in the main power well. Pull-ups must	signals are outputs only!
	use the 3.3 V plane.
	• Unused core well inputs must either be pulled up to
	VCC3.3 or be pulled down. These inputs must not be
	allowed to float.
	• GPIO[1:0] can be used as REQ[A:B]#.
	• GPIO[1] also can be used as PCI REQ[5]#.
	• These signals are 5 V tolerant.
	GPIO[8] & [11:13]:	These are the only GPI
	• These pins are in the resume power well. Pull-ups	signals in the resume well
		with associated status bits in
	must use the VCCSUS3.3 plane.
		the GPE1_STS register.
	• Unused resume well inputs must be pulled up to
	VCCSUS3.3.
	• These are the only GPIs that can be used as ACPI-
	compliant wake events.
	• These signals are not 5 V tolerant.
	GPIO[16:23]:
	• Fixed as output only. Can be left NC.
	• In the main power well
	• GPIO22 is open-drain.
	GPIO[24, 25, 27, 28]:
	• I/O pins. Can be left NC.
	• From resume power well

Table 33. USB Interface

Checklist Items	Recommendations	Reason/Effect
USBP[3:0]P	See Figure 56 for the circuitry needed on
USBP[3:0]N	each differential pair.

128 Design Guide