Intel 820E manual Copper Tab Area Calculation, Flood Signal

Intel® 820E Chipset

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The copper tab area for the recommended stack-up was determined by means of simulation. The amount of capacitance required is determined by the layer on which the RSL or clocking signal is routed. The copper tabs can be placed on any signal layer, independently of the layer on which the RSL signal is routed.

The following example calculation uses Equation 1. Approximate Copper Tab Area Calculation for a board with an ε r of 4.2 and a prepreg thickness of 4.5 mils. Note that these numbers vary with the difference in prepreg thickness.

Table 6. Copper Tab Area Calculation

Layer	Dielectric	Separation	Min.	Air Gap	Compensating	CTAB Area
	Thickness	Between	Ground	between	Capacitance in	(sq. mils)
		Signal Traces	Flood	Signal &	Cplate (pF)
		& Copper Tab		GND Flood
Top	4.5	6	10	6	0.65 – 0.85	~2810 – 3680
Bottom	4.5	6	10	6	1.20 – 1.40	~5194 – 6060

Note that more than one copper tab shape may be used, as shown in Figure 26. The dimensions are based on the copper area over the ground plane. The actual length and width of the tabs may differ due to routing constraints (e.g., if tab must extend to center of hole or anti-pad). Figures 26 through 28 show a tab compensation capacitor routing example. Note that the capacitor tabs must not interrupt ground floods around the RIMM pins, and they must be connected, to avoid discontinuity in the ground plane, as shown.

Figure 26. Top-Layer CTAB with RSL Signal Routed on the Same Layer (CEFF = 0.8 pF)

Figure 27. Bottom-Layer CTAB with RSL Signal Routed on the Same Layer (CEFF = 1.35 pF)

48 Design Guide