Intel 820E manual 3VSB, V and 2.5 V Power Sequencing Schottky Diode

Intel® 820E Chipset

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Figure 102. 1.8 V and 2.5 V Power Sequencing (Schottky Diode)

1.8 V

2.5 V

diode_1.8V&2.5V

VDDQ

The VDDQ plane is used to power the MCH AGP interface and the graphics component AGP interface. Refer to the AGP Interface Specification, Revision 2.0 (http://www.agpforum.org).

For long-term component reliability, the following power sequence is strongly recommended while the AGP interface of the MCH is running at 3.3 V. If the AGP interface is running at 1.5 V, the following power sequence recommendations no longer apply. The power sequence recommendations are as follows:

1.During the power-up sequence, the 1.8 V must ramp up to 1.0 V before the 3.3 V ramps up to 2.2 V.

2.During the power-down sequence, the 1.8 V cannot ramp below 1.0 V before the 3.3 V ramps below 2.2 V.

3.The same power sequence recommendation applies when entering and exiting the S3 state, because MCH power is completely off during the S3 state.

System designers must keep this requirement in mind while designing the voltage regulators and selecting the power supply. For further details regarding the voltage sequencing requirements, refer to the latest revision of the Intel® 820 Chipset: Intel® 82820 Memory Controller Hub (MCH) Datasheet (http://developer.intel.com/design/chipsets/datashts/290630.htm?iid=PCG+820blue&).

Note: This regulator is required in all designs (unless the design does not support 1.5 V AGP, and therefore does not support 4⋅ AGP).

3.3VSB

The 3.3 VSB plane powers the I/O buffers in the resume well of the ICH2 and the PCI 3.3 VAUX suspend power pins. The 3.3 VAUX requirement states that during suspend, the system must deliver 375 mA to each wake-enabledcard and 20 mA to each non-wake-enabledcard. During full-poweroperation, the system must be able to supply 375 mA to each card. Therefore, the total current requirement is as follows:

•Full-power operation: 375 mA ⋅ number of PCI slots

•Suspend operation: (375 + 20) ⋅ (number of PCI slots – 1)

In addition to the PCI 3.3 VAUX, the ICH2 suspend well power requirements must be considered, as shown in Error! Reference source not found..

Note: This regulator is required in all designs.

Design Guide 187