Intel® 820E Chipset

 

 

 

R

 

 

 

Table 34. Power Management

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Checklist Items

 

Recommendations

Reason/Effect

 

 

 

 

 

 

 

 

 

 

 

 

THRM#

 

Connect to temperature sensor.

Input to ICH2 cannot float. THRM#

 

 

 

 

 

 

Pull-up if not used.

polarity bit defaults THRM# to active

 

 

 

 

 

 

 

low, so pull-up.

 

 

 

 

 

 

 

 

 

 

 

 

SLP_S3#

 

No pull-up/pull-down resistors needed.

Signal driven by ICH2.

 

 

 

 

SLP_S5#

 

Signals driven by ICH2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWROK

 

This signal should be connected to power

Timing requirement

 

 

 

 

 

 

monitoring logic, and should go high no

 

 

 

 

 

 

 

sooner than 10 ms after both Vcc 3_3 and

 

 

 

 

 

 

 

Vcc 1_8 have reached their nominal

 

 

 

 

 

 

 

voltages

 

 

 

 

 

 

 

 

 

 

 

 

 

PWRBTN#

 

No extra pull-up resistors

This signal has an integrated pull-up of 9

 

 

 

 

 

 

 

k± 3 k.

 

 

 

 

 

 

 

 

 

 

 

 

RI#

 

RI# does not have an internal pull-up. An

If this signal is enabled as a wake event,

 

 

 

 

 

 

8.2 kpull-up resistor to the resume well is

it is important to keep it powered during

 

 

 

 

 

 

recommended.

the power loss event. If this signal goes

 

 

 

 

 

 

 

low (active), when power returns the

 

 

 

 

 

 

 

RI_STS bit will be set and the system

 

 

 

 

 

 

 

will interpret that as a wake event.

 

 

 

 

 

 

 

 

 

 

 

 

RSMRST#

 

This signal should be connected to power

Timing requirement

 

 

 

 

 

 

monitoring logic, and it should go high no

 

 

 

 

 

 

 

sooner than 10 ms after both VccSus3_3

 

 

 

 

 

 

 

and VccSus1_8 have reached their nominal

 

 

 

 

 

 

 

voltages. It can be tied to RESUMEPWROK

 

 

 

 

 

 

 

on desktop platforms.

 

 

 

 

 

 

Table 35. Processor Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Checklist Items

 

Recommendations

Reason/Effect

 

 

 

 

 

 

 

 

 

 

 

 

A20M#, CPUSLP#,

 

Internal circuitry has been added to the

Push/pull buffers now drive the output

 

 

 

 

IGNNE#, INIT#, INTR,

 

ICH2. External pull-up resistors are not

signals.

 

 

 

 

NMI, SMI#, STPCLK#

 

needed.

 

 

 

 

 

 

 

 

 

 

 

 

 

FERR#

 

Requires a weak external pull-up resistor

For specific values, refer to the

 

 

 

 

 

 

to VCCCORE.

processor documentation for the

 

 

 

 

 

 

 

processor that the platform utilizes.

 

 

 

 

 

 

 

 

 

 

 

 

RCIN#

 

Pull-up signals to VCC 3.3 through a 10 k

Typically driven by an open-drain

 

 

 

 

A20GATE

 

resistor

external microcontroller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPUPWRGD

 

Connect to the processor PWRGOOD

For specific values, refer to the

 

 

 

 

 

 

input. Requires a weak external pull-up

processor documentation for the

 

 

 

 

 

 

resistor to VCCCORE.

processor that the platform utilizes.

 

 

 

 

 

 

 

 

Design Guide

129

Page 129
Image 129
Intel 820E manual Processor Signals